[1141c1a] | 1 | /*
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[df4ed85] | 2 | * Copyright (c) 2005 Ondrej Palkovsky
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[1141c1a] | 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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[7f1c620] | 29 | /** @addtogroup amd64mm
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[b45c443] | 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | */
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| 34 |
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[93165be] | 35 | /** Paging on AMD64
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| 36 | *
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[a1f60f3] | 37 | * The space is divided in positive numbers (uspace) and
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| 38 | * negative numbers (kernel). The 'negative' space starting
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| 39 | * with 0xffff800000000000 and ending with 0xffffffffffffffff
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| 40 | * is identically mapped physical memory.
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[93165be] | 41 | *
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| 42 | */
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| 43 |
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[06e1e95] | 44 | #ifndef KERN_amd64_PAGE_H_
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| 45 | #define KERN_amd64_PAGE_H_
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[1141c1a] | 46 |
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[fa2d382] | 47 | #include <arch/mm/frame.h>
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| 48 |
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[a1f60f3] | 49 | #define PAGE_WIDTH FRAME_WIDTH
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| 50 | #define PAGE_SIZE FRAME_SIZE
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[d1f8a87] | 51 |
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| 52 | #ifdef KERNEL
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| 53 |
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[8fc0d455] | 54 | #ifndef __ASM__
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[1141c1a] | 55 |
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[a1f60f3] | 56 | #define KA2PA(x) (((uintptr_t) (x)) - 0xffff800000000000)
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| 57 | #define PA2KA(x) (((uintptr_t) (x)) + 0xffff800000000000)
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[b3f8fb7] | 58 |
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[a1f60f3] | 59 | #else /* __ASM__ */
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| 60 |
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| 61 | #define KA2PA(x) ((x) - 0xffff800000000000)
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| 62 | #define PA2KA(x) ((x) + 0xffff800000000000)
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| 63 |
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| 64 | #endif /* __ASM__ */
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[8fc0d455] | 65 |
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[c03ee1c] | 66 | /* Number of entries in each level. */
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[a1f60f3] | 67 | #define PTL0_ENTRIES_ARCH 512
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| 68 | #define PTL1_ENTRIES_ARCH 512
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| 69 | #define PTL2_ENTRIES_ARCH 512
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| 70 | #define PTL3_ENTRIES_ARCH 512
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[ecbdc724] | 71 |
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[c03ee1c] | 72 | /* Page table sizes for each level. */
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[a1f60f3] | 73 | #define PTL0_SIZE_ARCH ONE_FRAME
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| 74 | #define PTL1_SIZE_ARCH ONE_FRAME
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| 75 | #define PTL2_SIZE_ARCH ONE_FRAME
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| 76 | #define PTL3_SIZE_ARCH ONE_FRAME
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[c03ee1c] | 77 |
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| 78 | /* Macros calculating indices into page tables in each level. */
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[a1f60f3] | 79 | #define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 39) & 0x1ff)
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| 80 | #define PTL1_INDEX_ARCH(vaddr) (((vaddr) >> 30) & 0x1ff)
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| 81 | #define PTL2_INDEX_ARCH(vaddr) (((vaddr) >> 21) & 0x1ff)
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| 82 | #define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x1ff)
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[c03ee1c] | 83 |
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| 84 | /* Get PTE address accessors for each level. */
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| 85 | #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
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| 86 | ((pte_t *) ((((uint64_t) ((pte_t *) (ptl0))[(i)].addr_12_31) << 12) | \
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| 87 | (((uint64_t) ((pte_t *) (ptl0))[(i)].addr_32_51) << 32)))
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| 88 | #define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
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| 89 | ((pte_t *) ((((uint64_t) ((pte_t *) (ptl1))[(i)].addr_12_31) << 12) | \
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| 90 | (((uint64_t) ((pte_t *) (ptl1))[(i)].addr_32_51) << 32)))
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| 91 | #define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
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| 92 | ((pte_t *) ((((uint64_t) ((pte_t *) (ptl2))[(i)].addr_12_31) << 12) | \
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| 93 | (((uint64_t) ((pte_t *) (ptl2))[(i)].addr_32_51) << 32)))
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| 94 | #define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
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| 95 | ((uintptr_t *) \
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| 96 | ((((uint64_t) ((pte_t *) (ptl3))[(i)].addr_12_31) << 12) | \
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| 97 | (((uint64_t) ((pte_t *) (ptl3))[(i)].addr_32_51) << 32)))
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| 98 |
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| 99 | /* Set PTE address accessors for each level. */
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| 100 | #define SET_PTL0_ADDRESS_ARCH(ptl0) \
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| 101 | (write_cr3((uintptr_t) (ptl0)))
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| 102 | #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
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[98000fb] | 103 | set_pt_addr((pte_t *) (ptl0), (size_t) (i), a)
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[c03ee1c] | 104 | #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) \
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[98000fb] | 105 | set_pt_addr((pte_t *) (ptl1), (size_t) (i), a)
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[c03ee1c] | 106 | #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) \
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[98000fb] | 107 | set_pt_addr((pte_t *) (ptl2), (size_t) (i), a)
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[c03ee1c] | 108 | #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
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[98000fb] | 109 | set_pt_addr((pte_t *) (ptl3), (size_t) (i), a)
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[c03ee1c] | 110 |
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| 111 | /* Get PTE flags accessors for each level. */
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| 112 | #define GET_PTL1_FLAGS_ARCH(ptl0, i) \
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[98000fb] | 113 | get_pt_flags((pte_t *) (ptl0), (size_t) (i))
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[c03ee1c] | 114 | #define GET_PTL2_FLAGS_ARCH(ptl1, i) \
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[98000fb] | 115 | get_pt_flags((pte_t *) (ptl1), (size_t) (i))
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[c03ee1c] | 116 | #define GET_PTL3_FLAGS_ARCH(ptl2, i) \
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[98000fb] | 117 | get_pt_flags((pte_t *) (ptl2), (size_t) (i))
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[c03ee1c] | 118 | #define GET_FRAME_FLAGS_ARCH(ptl3, i) \
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[98000fb] | 119 | get_pt_flags((pte_t *) (ptl3), (size_t) (i))
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[c03ee1c] | 120 |
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| 121 | /* Set PTE flags accessors for each level. */
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| 122 | #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
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[98000fb] | 123 | set_pt_flags((pte_t *) (ptl0), (size_t) (i), (x))
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[c03ee1c] | 124 | #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) \
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[98000fb] | 125 | set_pt_flags((pte_t *) (ptl1), (size_t) (i), (x))
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[c03ee1c] | 126 | #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) \
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[98000fb] | 127 | set_pt_flags((pte_t *) (ptl2), (size_t) (i), (x))
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[c03ee1c] | 128 | #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
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[98000fb] | 129 | set_pt_flags((pte_t *) (ptl3), (size_t) (i), (x))
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[c03ee1c] | 130 |
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| 131 | /* Macros for querying the last-level PTE entries. */
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| 132 | #define PTE_VALID_ARCH(p) \
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| 133 | (*((uint64_t *) (p)) != 0)
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| 134 | #define PTE_PRESENT_ARCH(p) \
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| 135 | ((p)->present != 0)
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| 136 | #define PTE_GET_FRAME_ARCH(p) \
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| 137 | ((((uintptr_t) (p)->addr_12_31) << 12) | \
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| 138 | ((uintptr_t) (p)->addr_32_51 << 32))
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| 139 | #define PTE_WRITABLE_ARCH(p) \
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| 140 | ((p)->writeable != 0)
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| 141 | #define PTE_EXECUTABLE_ARCH(p) \
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| 142 | ((p)->no_execute == 0)
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[ecbdc724] | 143 |
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[8fc0d455] | 144 | #ifndef __ASM__
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[db3341e] | 145 |
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[a1f60f3] | 146 | #include <mm/mm.h>
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| 147 | #include <arch/interrupt.h>
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| 148 | #include <typedefs.h>
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| 149 |
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[567807b1] | 150 | /* Page fault error codes. */
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| 151 |
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[c03ee1c] | 152 | /** When bit on this position is 0, the page fault was caused by a not-present
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| 153 | * page.
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| 154 | */
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[a1f60f3] | 155 | #define PFERR_CODE_P (1 << 0)
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[567807b1] | 156 |
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| 157 | /** When bit on this position is 1, the page fault was caused by a write. */
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[a1f60f3] | 158 | #define PFERR_CODE_RW (1 << 1)
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[567807b1] | 159 |
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| 160 | /** When bit on this position is 1, the page fault was caused in user mode. */
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[a1f60f3] | 161 | #define PFERR_CODE_US (1 << 2)
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[567807b1] | 162 |
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| 163 | /** When bit on this position is 1, a reserved bit was set in page directory. */
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[a1f60f3] | 164 | #define PFERR_CODE_RSVD (1 << 3)
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[567807b1] | 165 |
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[c03ee1c] | 166 | /** When bit on this position os 1, the page fault was caused during instruction
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| 167 | * fecth.
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| 168 | */
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[a1f60f3] | 169 | #define PFERR_CODE_ID (1 << 4)
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[567807b1] | 170 |
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[33be9ac] | 171 | /** Page Table Entry. */
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| 172 | typedef struct {
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[a1f60f3] | 173 | unsigned int present : 1;
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| 174 | unsigned int writeable : 1;
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| 175 | unsigned int uaccessible : 1;
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| 176 | unsigned int page_write_through : 1;
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| 177 | unsigned int page_cache_disable : 1;
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| 178 | unsigned int accessed : 1;
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| 179 | unsigned int dirty : 1;
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| 180 | unsigned int unused: 1;
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| 181 | unsigned int global : 1;
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| 182 | unsigned int soft_valid : 1; /**< Valid content even if present bit is cleared. */
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| 183 | unsigned int avl : 2;
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| 184 | unsigned int addr_12_31 : 30;
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| 185 | unsigned int addr_32_51 : 21;
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| 186 | unsigned int no_execute : 1;
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[33be9ac] | 187 | } __attribute__ ((packed)) pte_t;
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| 188 |
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[a217358] | 189 | static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
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[db3341e] | 190 | {
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| 191 | pte_t *p = &pt[i];
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| 192 |
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[c03ee1c] | 193 | return ((!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT |
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| 194 | (!p->present) << PAGE_PRESENT_SHIFT |
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| 195 | p->uaccessible << PAGE_USER_SHIFT |
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| 196 | 1 << PAGE_READ_SHIFT |
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| 197 | p->writeable << PAGE_WRITE_SHIFT |
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| 198 | (!p->no_execute) << PAGE_EXEC_SHIFT |
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| 199 | p->global << PAGE_GLOBAL_SHIFT);
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[db3341e] | 200 | }
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| 201 |
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[98000fb] | 202 | static inline void set_pt_addr(pte_t *pt, size_t i, uintptr_t a)
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[db3341e] | 203 | {
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| 204 | pte_t *p = &pt[i];
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[a1f60f3] | 205 |
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[db3341e] | 206 | p->addr_12_31 = (a >> 12) & 0xfffff;
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| 207 | p->addr_32_51 = a >> 32;
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| 208 | }
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| 209 |
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[98000fb] | 210 | static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
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[db3341e] | 211 | {
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| 212 | pte_t *p = &pt[i];
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| 213 |
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| 214 | p->page_cache_disable = !(flags & PAGE_CACHEABLE);
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| 215 | p->present = !(flags & PAGE_NOT_PRESENT);
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| 216 | p->uaccessible = (flags & PAGE_USER) != 0;
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| 217 | p->writeable = (flags & PAGE_WRITE) != 0;
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| 218 | p->no_execute = (flags & PAGE_EXEC) == 0;
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[bfb87df] | 219 | p->global = (flags & PAGE_GLOBAL) != 0;
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[0882a9a] | 220 |
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| 221 | /*
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| 222 | * Ensure that there is at least one bit set even if the present bit is cleared.
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| 223 | */
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| 224 | p->soft_valid = 1;
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[db3341e] | 225 | }
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| 226 |
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[1141c1a] | 227 | extern void page_arch_init(void);
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[214ec25c] | 228 | extern void page_fault(unsigned int, istate_t *);
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[1141c1a] | 229 |
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[d1f8a87] | 230 | #endif /* __ASM__ */
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| 231 |
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| 232 | #endif /* KERNEL */
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[1141c1a] | 233 |
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| 234 | #endif
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[b45c443] | 235 |
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[7f1c620] | 236 | /** @}
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[b45c443] | 237 | */
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