source: mainline/kernel/arch/amd64/include/mm/page.h@ cefb126

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since cefb126 was a1f60f3, checked in by Martin Decky <martin@…>, 15 years ago

move from "kernel" memory model to "large" memory model
get rid of the extra identity mapping of the physical memory at -2 GB

  • Property mode set to 100644
File size: 7.5 KB
RevLine 
[1141c1a]1/*
[df4ed85]2 * Copyright (c) 2005 Ondrej Palkovsky
[1141c1a]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[7f1c620]29/** @addtogroup amd64mm
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[93165be]35/** Paging on AMD64
36 *
[a1f60f3]37 * The space is divided in positive numbers (uspace) and
38 * negative numbers (kernel). The 'negative' space starting
39 * with 0xffff800000000000 and ending with 0xffffffffffffffff
40 * is identically mapped physical memory.
[93165be]41 *
42 */
43
[06e1e95]44#ifndef KERN_amd64_PAGE_H_
45#define KERN_amd64_PAGE_H_
[1141c1a]46
[fa2d382]47#include <arch/mm/frame.h>
48
[a1f60f3]49#define PAGE_WIDTH FRAME_WIDTH
50#define PAGE_SIZE FRAME_SIZE
[d1f8a87]51
52#ifdef KERNEL
53
[8fc0d455]54#ifndef __ASM__
[1141c1a]55
[a1f60f3]56#define KA2PA(x) (((uintptr_t) (x)) - 0xffff800000000000)
57#define PA2KA(x) (((uintptr_t) (x)) + 0xffff800000000000)
[b3f8fb7]58
[a1f60f3]59#else /* __ASM__ */
60
61#define KA2PA(x) ((x) - 0xffff800000000000)
62#define PA2KA(x) ((x) + 0xffff800000000000)
63
64#endif /* __ASM__ */
[8fc0d455]65
[c03ee1c]66/* Number of entries in each level. */
[a1f60f3]67#define PTL0_ENTRIES_ARCH 512
68#define PTL1_ENTRIES_ARCH 512
69#define PTL2_ENTRIES_ARCH 512
70#define PTL3_ENTRIES_ARCH 512
[ecbdc724]71
[c03ee1c]72/* Page table sizes for each level. */
[a1f60f3]73#define PTL0_SIZE_ARCH ONE_FRAME
74#define PTL1_SIZE_ARCH ONE_FRAME
75#define PTL2_SIZE_ARCH ONE_FRAME
76#define PTL3_SIZE_ARCH ONE_FRAME
[c03ee1c]77
78/* Macros calculating indices into page tables in each level. */
[a1f60f3]79#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 39) & 0x1ff)
80#define PTL1_INDEX_ARCH(vaddr) (((vaddr) >> 30) & 0x1ff)
81#define PTL2_INDEX_ARCH(vaddr) (((vaddr) >> 21) & 0x1ff)
82#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x1ff)
[c03ee1c]83
84/* Get PTE address accessors for each level. */
85#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
86 ((pte_t *) ((((uint64_t) ((pte_t *) (ptl0))[(i)].addr_12_31) << 12) | \
87 (((uint64_t) ((pte_t *) (ptl0))[(i)].addr_32_51) << 32)))
88#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
89 ((pte_t *) ((((uint64_t) ((pte_t *) (ptl1))[(i)].addr_12_31) << 12) | \
90 (((uint64_t) ((pte_t *) (ptl1))[(i)].addr_32_51) << 32)))
91#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
92 ((pte_t *) ((((uint64_t) ((pte_t *) (ptl2))[(i)].addr_12_31) << 12) | \
93 (((uint64_t) ((pte_t *) (ptl2))[(i)].addr_32_51) << 32)))
94#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
95 ((uintptr_t *) \
96 ((((uint64_t) ((pte_t *) (ptl3))[(i)].addr_12_31) << 12) | \
97 (((uint64_t) ((pte_t *) (ptl3))[(i)].addr_32_51) << 32)))
98
99/* Set PTE address accessors for each level. */
100#define SET_PTL0_ADDRESS_ARCH(ptl0) \
101 (write_cr3((uintptr_t) (ptl0)))
102#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
[98000fb]103 set_pt_addr((pte_t *) (ptl0), (size_t) (i), a)
[c03ee1c]104#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) \
[98000fb]105 set_pt_addr((pte_t *) (ptl1), (size_t) (i), a)
[c03ee1c]106#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) \
[98000fb]107 set_pt_addr((pte_t *) (ptl2), (size_t) (i), a)
[c03ee1c]108#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
[98000fb]109 set_pt_addr((pte_t *) (ptl3), (size_t) (i), a)
[c03ee1c]110
111/* Get PTE flags accessors for each level. */
112#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
[98000fb]113 get_pt_flags((pte_t *) (ptl0), (size_t) (i))
[c03ee1c]114#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
[98000fb]115 get_pt_flags((pte_t *) (ptl1), (size_t) (i))
[c03ee1c]116#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
[98000fb]117 get_pt_flags((pte_t *) (ptl2), (size_t) (i))
[c03ee1c]118#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
[98000fb]119 get_pt_flags((pte_t *) (ptl3), (size_t) (i))
[c03ee1c]120
121/* Set PTE flags accessors for each level. */
122#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
[98000fb]123 set_pt_flags((pte_t *) (ptl0), (size_t) (i), (x))
[c03ee1c]124#define SET_PTL2_FLAGS_ARCH(ptl1, i, x) \
[98000fb]125 set_pt_flags((pte_t *) (ptl1), (size_t) (i), (x))
[c03ee1c]126#define SET_PTL3_FLAGS_ARCH(ptl2, i, x) \
[98000fb]127 set_pt_flags((pte_t *) (ptl2), (size_t) (i), (x))
[c03ee1c]128#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
[98000fb]129 set_pt_flags((pte_t *) (ptl3), (size_t) (i), (x))
[c03ee1c]130
131/* Macros for querying the last-level PTE entries. */
132#define PTE_VALID_ARCH(p) \
133 (*((uint64_t *) (p)) != 0)
134#define PTE_PRESENT_ARCH(p) \
135 ((p)->present != 0)
136#define PTE_GET_FRAME_ARCH(p) \
137 ((((uintptr_t) (p)->addr_12_31) << 12) | \
138 ((uintptr_t) (p)->addr_32_51 << 32))
139#define PTE_WRITABLE_ARCH(p) \
140 ((p)->writeable != 0)
141#define PTE_EXECUTABLE_ARCH(p) \
142 ((p)->no_execute == 0)
[ecbdc724]143
[8fc0d455]144#ifndef __ASM__
[db3341e]145
[a1f60f3]146#include <mm/mm.h>
147#include <arch/interrupt.h>
148#include <typedefs.h>
149
[567807b1]150/* Page fault error codes. */
151
[c03ee1c]152/** When bit on this position is 0, the page fault was caused by a not-present
153 * page.
154 */
[a1f60f3]155#define PFERR_CODE_P (1 << 0)
[567807b1]156
157/** When bit on this position is 1, the page fault was caused by a write. */
[a1f60f3]158#define PFERR_CODE_RW (1 << 1)
[567807b1]159
160/** When bit on this position is 1, the page fault was caused in user mode. */
[a1f60f3]161#define PFERR_CODE_US (1 << 2)
[567807b1]162
163/** When bit on this position is 1, a reserved bit was set in page directory. */
[a1f60f3]164#define PFERR_CODE_RSVD (1 << 3)
[567807b1]165
[c03ee1c]166/** When bit on this position os 1, the page fault was caused during instruction
167 * fecth.
168 */
[a1f60f3]169#define PFERR_CODE_ID (1 << 4)
[567807b1]170
[33be9ac]171/** Page Table Entry. */
172typedef struct {
[a1f60f3]173 unsigned int present : 1;
174 unsigned int writeable : 1;
175 unsigned int uaccessible : 1;
176 unsigned int page_write_through : 1;
177 unsigned int page_cache_disable : 1;
178 unsigned int accessed : 1;
179 unsigned int dirty : 1;
180 unsigned int unused: 1;
181 unsigned int global : 1;
182 unsigned int soft_valid : 1; /**< Valid content even if present bit is cleared. */
183 unsigned int avl : 2;
184 unsigned int addr_12_31 : 30;
185 unsigned int addr_32_51 : 21;
186 unsigned int no_execute : 1;
[33be9ac]187} __attribute__ ((packed)) pte_t;
188
[a217358]189static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
[db3341e]190{
191 pte_t *p = &pt[i];
192
[c03ee1c]193 return ((!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT |
194 (!p->present) << PAGE_PRESENT_SHIFT |
195 p->uaccessible << PAGE_USER_SHIFT |
196 1 << PAGE_READ_SHIFT |
197 p->writeable << PAGE_WRITE_SHIFT |
198 (!p->no_execute) << PAGE_EXEC_SHIFT |
199 p->global << PAGE_GLOBAL_SHIFT);
[db3341e]200}
201
[98000fb]202static inline void set_pt_addr(pte_t *pt, size_t i, uintptr_t a)
[db3341e]203{
204 pte_t *p = &pt[i];
[a1f60f3]205
[db3341e]206 p->addr_12_31 = (a >> 12) & 0xfffff;
207 p->addr_32_51 = a >> 32;
208}
209
[98000fb]210static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
[db3341e]211{
212 pte_t *p = &pt[i];
213
214 p->page_cache_disable = !(flags & PAGE_CACHEABLE);
215 p->present = !(flags & PAGE_NOT_PRESENT);
216 p->uaccessible = (flags & PAGE_USER) != 0;
217 p->writeable = (flags & PAGE_WRITE) != 0;
218 p->no_execute = (flags & PAGE_EXEC) == 0;
[bfb87df]219 p->global = (flags & PAGE_GLOBAL) != 0;
[0882a9a]220
221 /*
222 * Ensure that there is at least one bit set even if the present bit is cleared.
223 */
224 p->soft_valid = 1;
[db3341e]225}
226
[1141c1a]227extern void page_arch_init(void);
[214ec25c]228extern void page_fault(unsigned int, istate_t *);
[1141c1a]229
[d1f8a87]230#endif /* __ASM__ */
231
232#endif /* KERNEL */
[1141c1a]233
234#endif
[b45c443]235
[7f1c620]236/** @}
[b45c443]237 */
Note: See TracBrowser for help on using the repository browser.