[1141c1a] | 1 | /*
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[df4ed85] | 2 | * Copyright (c) 2005 Ondrej Palkovsky
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[1141c1a] | 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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[7f1c620] | 29 | /** @addtogroup amd64mm
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[b45c443] | 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | */
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| 34 |
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[93165be] | 35 | /** Paging on AMD64
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| 36 | *
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| 37 | * The space is divided in positive numbers - userspace and
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| 38 | * negative numbers - kernel space. The 'negative' space starting
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| 39 | * with 0xffff800000000000 and ending with 0xffffffff80000000
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| 40 | * (-2GB) is identically mapped physical memory. The area
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| 41 | * (0xffffffff80000000 ... 0xffffffffffffffff is again identically
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| 42 | * mapped first 2GB.
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| 43 | *
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| 44 | * ATTENTION - PA2KA(KA2PA(x)) != x if 'x' is in kernel
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| 45 | */
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| 46 |
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[06e1e95] | 47 | #ifndef KERN_amd64_PAGE_H_
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| 48 | #define KERN_amd64_PAGE_H_
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[1141c1a] | 49 |
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[fa2d382] | 50 | #include <arch/mm/frame.h>
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| 51 |
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[d1f8a87] | 52 | #define PAGE_WIDTH FRAME_WIDTH
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| 53 | #define PAGE_SIZE FRAME_SIZE
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| 54 |
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[d0485c6] | 55 | #define PAGE_COLOR_BITS 0 /* dummy */
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| 56 |
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[d1f8a87] | 57 | #ifdef KERNEL
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| 58 |
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[8fc0d455] | 59 | #ifndef __ASM__
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[b3f8fb7] | 60 | # include <mm/mm.h>
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| 61 | # include <arch/types.h>
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| 62 | # include <arch/interrupt.h>
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[1141c1a] | 63 |
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[7f1c620] | 64 | static inline uintptr_t ka2pa(uintptr_t x)
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[93165be] | 65 | {
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| 66 | if (x > 0xffffffff80000000)
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| 67 | return x - 0xffffffff80000000;
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| 68 | else
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| 69 | return x - 0xffff800000000000;
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| 70 | }
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[b3f8fb7] | 71 |
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[c03ee1c] | 72 | # define KA2PA(x) ka2pa((uintptr_t) x)
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| 73 | # define PA2KA_CODE(x) (((uintptr_t) (x)) + 0xffffffff80000000)
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| 74 | # define PA2KA(x) (((uintptr_t) (x)) + 0xffff800000000000)
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[8fc0d455] | 75 | #else
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[c03ee1c] | 76 | # define KA2PA(x) ((x) - 0xffffffff80000000)
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| 77 | # define PA2KA(x) ((x) + 0xffffffff80000000)
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[8fc0d455] | 78 | #endif
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| 79 |
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[c03ee1c] | 80 | /* Number of entries in each level. */
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[ecbdc724] | 81 | #define PTL0_ENTRIES_ARCH 512
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| 82 | #define PTL1_ENTRIES_ARCH 512
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| 83 | #define PTL2_ENTRIES_ARCH 512
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| 84 | #define PTL3_ENTRIES_ARCH 512
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| 85 |
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[c03ee1c] | 86 | /* Page table sizes for each level. */
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| 87 | #define PTL0_SIZE_ARCH ONE_FRAME
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| 88 | #define PTL1_SIZE_ARCH ONE_FRAME
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| 89 | #define PTL2_SIZE_ARCH ONE_FRAME
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| 90 | #define PTL3_SIZE_ARCH ONE_FRAME
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| 91 |
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| 92 | /* Macros calculating indices into page tables in each level. */
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| 93 | #define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 39) & 0x1ff)
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| 94 | #define PTL1_INDEX_ARCH(vaddr) (((vaddr) >> 30) & 0x1ff)
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| 95 | #define PTL2_INDEX_ARCH(vaddr) (((vaddr) >> 21) & 0x1ff)
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| 96 | #define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x1ff)
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| 97 |
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| 98 | /* Get PTE address accessors for each level. */
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| 99 | #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
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| 100 | ((pte_t *) ((((uint64_t) ((pte_t *) (ptl0))[(i)].addr_12_31) << 12) | \
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| 101 | (((uint64_t) ((pte_t *) (ptl0))[(i)].addr_32_51) << 32)))
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| 102 | #define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
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| 103 | ((pte_t *) ((((uint64_t) ((pte_t *) (ptl1))[(i)].addr_12_31) << 12) | \
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| 104 | (((uint64_t) ((pte_t *) (ptl1))[(i)].addr_32_51) << 32)))
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| 105 | #define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
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| 106 | ((pte_t *) ((((uint64_t) ((pte_t *) (ptl2))[(i)].addr_12_31) << 12) | \
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| 107 | (((uint64_t) ((pte_t *) (ptl2))[(i)].addr_32_51) << 32)))
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| 108 | #define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
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| 109 | ((uintptr_t *) \
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| 110 | ((((uint64_t) ((pte_t *) (ptl3))[(i)].addr_12_31) << 12) | \
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| 111 | (((uint64_t) ((pte_t *) (ptl3))[(i)].addr_32_51) << 32)))
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| 112 |
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| 113 | /* Set PTE address accessors for each level. */
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| 114 | #define SET_PTL0_ADDRESS_ARCH(ptl0) \
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| 115 | (write_cr3((uintptr_t) (ptl0)))
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| 116 | #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
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| 117 | set_pt_addr((pte_t *) (ptl0), (index_t) (i), a)
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| 118 | #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) \
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| 119 | set_pt_addr((pte_t *) (ptl1), (index_t) (i), a)
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| 120 | #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) \
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| 121 | set_pt_addr((pte_t *) (ptl2), (index_t) (i), a)
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| 122 | #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
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| 123 | set_pt_addr((pte_t *) (ptl3), (index_t) (i), a)
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| 124 |
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| 125 | /* Get PTE flags accessors for each level. */
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| 126 | #define GET_PTL1_FLAGS_ARCH(ptl0, i) \
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| 127 | get_pt_flags((pte_t *) (ptl0), (index_t) (i))
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| 128 | #define GET_PTL2_FLAGS_ARCH(ptl1, i) \
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| 129 | get_pt_flags((pte_t *) (ptl1), (index_t) (i))
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| 130 | #define GET_PTL3_FLAGS_ARCH(ptl2, i) \
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| 131 | get_pt_flags((pte_t *) (ptl2), (index_t) (i))
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| 132 | #define GET_FRAME_FLAGS_ARCH(ptl3, i) \
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| 133 | get_pt_flags((pte_t *) (ptl3), (index_t) (i))
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| 134 |
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| 135 | /* Set PTE flags accessors for each level. */
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| 136 | #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
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| 137 | set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x))
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| 138 | #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) \
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| 139 | set_pt_flags((pte_t *) (ptl1), (index_t) (i), (x))
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| 140 | #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) \
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| 141 | set_pt_flags((pte_t *) (ptl2), (index_t) (i), (x))
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| 142 | #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
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| 143 | set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x))
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| 144 |
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| 145 | /* Macros for querying the last-level PTE entries. */
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| 146 | #define PTE_VALID_ARCH(p) \
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| 147 | (*((uint64_t *) (p)) != 0)
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| 148 | #define PTE_PRESENT_ARCH(p) \
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| 149 | ((p)->present != 0)
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| 150 | #define PTE_GET_FRAME_ARCH(p) \
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| 151 | ((((uintptr_t) (p)->addr_12_31) << 12) | \
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| 152 | ((uintptr_t) (p)->addr_32_51 << 32))
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| 153 | #define PTE_WRITABLE_ARCH(p) \
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| 154 | ((p)->writeable != 0)
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| 155 | #define PTE_EXECUTABLE_ARCH(p) \
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| 156 | ((p)->no_execute == 0)
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[ecbdc724] | 157 |
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[8fc0d455] | 158 | #ifndef __ASM__
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[db3341e] | 159 |
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[567807b1] | 160 | /* Page fault error codes. */
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| 161 |
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[c03ee1c] | 162 | /** When bit on this position is 0, the page fault was caused by a not-present
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| 163 | * page.
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| 164 | */
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| 165 | #define PFERR_CODE_P (1 << 0)
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[567807b1] | 166 |
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| 167 | /** When bit on this position is 1, the page fault was caused by a write. */
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[c03ee1c] | 168 | #define PFERR_CODE_RW (1 << 1)
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[567807b1] | 169 |
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| 170 | /** When bit on this position is 1, the page fault was caused in user mode. */
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[c03ee1c] | 171 | #define PFERR_CODE_US (1 << 2)
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[567807b1] | 172 |
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| 173 | /** When bit on this position is 1, a reserved bit was set in page directory. */
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[c03ee1c] | 174 | #define PFERR_CODE_RSVD (1 << 3)
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[567807b1] | 175 |
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[c03ee1c] | 176 | /** When bit on this position os 1, the page fault was caused during instruction
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| 177 | * fecth.
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| 178 | */
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| 179 | #define PFERR_CODE_ID (1 << 4)
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[567807b1] | 180 |
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[db3341e] | 181 | static inline int get_pt_flags(pte_t *pt, index_t i)
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| 182 | {
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| 183 | pte_t *p = &pt[i];
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| 184 |
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[c03ee1c] | 185 | return ((!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT |
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| 186 | (!p->present) << PAGE_PRESENT_SHIFT |
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| 187 | p->uaccessible << PAGE_USER_SHIFT |
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| 188 | 1 << PAGE_READ_SHIFT |
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| 189 | p->writeable << PAGE_WRITE_SHIFT |
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| 190 | (!p->no_execute) << PAGE_EXEC_SHIFT |
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| 191 | p->global << PAGE_GLOBAL_SHIFT);
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[db3341e] | 192 | }
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| 193 |
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[7f1c620] | 194 | static inline void set_pt_addr(pte_t *pt, index_t i, uintptr_t a)
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[db3341e] | 195 | {
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| 196 | pte_t *p = &pt[i];
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| 197 |
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| 198 | p->addr_12_31 = (a >> 12) & 0xfffff;
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| 199 | p->addr_32_51 = a >> 32;
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| 200 | }
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| 201 |
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| 202 | static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
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| 203 | {
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| 204 | pte_t *p = &pt[i];
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| 205 |
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| 206 | p->page_cache_disable = !(flags & PAGE_CACHEABLE);
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| 207 | p->present = !(flags & PAGE_NOT_PRESENT);
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| 208 | p->uaccessible = (flags & PAGE_USER) != 0;
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| 209 | p->writeable = (flags & PAGE_WRITE) != 0;
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| 210 | p->no_execute = (flags & PAGE_EXEC) == 0;
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[bfb87df] | 211 | p->global = (flags & PAGE_GLOBAL) != 0;
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[0882a9a] | 212 |
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| 213 | /*
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| 214 | * Ensure that there is at least one bit set even if the present bit is cleared.
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| 215 | */
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| 216 | p->soft_valid = 1;
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[db3341e] | 217 | }
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| 218 |
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[1141c1a] | 219 | extern void page_arch_init(void);
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[8607db8] | 220 | extern void page_fault(int n, istate_t *istate);
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[1141c1a] | 221 |
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[d1f8a87] | 222 | #endif /* __ASM__ */
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| 223 |
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| 224 | #endif /* KERNEL */
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[1141c1a] | 225 |
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| 226 | #endif
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[b45c443] | 227 |
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[7f1c620] | 228 | /** @}
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[b45c443] | 229 | */
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