source: mainline/kernel/arch/amd64/include/mm/page.h@ af103f4

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since af103f4 was dc0b964, checked in by Martin Decky <martin@…>, 15 years ago
  • do not hardwire PRI??? formatting macros in the sources, use autotool to detect the correct values
  • use autotool to detect correct values for integer literal macros (UINT32_C, etc.)
  • start using portable UINT??_C style macros for integer constants
  • Property mode set to 100644
File size: 7.6 KB
RevLine 
[1141c1a]1/*
[df4ed85]2 * Copyright (c) 2005 Ondrej Palkovsky
[1141c1a]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[7f1c620]29/** @addtogroup amd64mm
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[93165be]35/** Paging on AMD64
36 *
[a1f60f3]37 * The space is divided in positive numbers (uspace) and
38 * negative numbers (kernel). The 'negative' space starting
39 * with 0xffff800000000000 and ending with 0xffffffffffffffff
40 * is identically mapped physical memory.
[93165be]41 *
42 */
43
[06e1e95]44#ifndef KERN_amd64_PAGE_H_
45#define KERN_amd64_PAGE_H_
[1141c1a]46
[fa2d382]47#include <arch/mm/frame.h>
[7a0359b]48#include <trace.h>
[fa2d382]49
[a1f60f3]50#define PAGE_WIDTH FRAME_WIDTH
51#define PAGE_SIZE FRAME_SIZE
[d1f8a87]52
53#ifdef KERNEL
54
[8fc0d455]55#ifndef __ASM__
[1141c1a]56
[dc0b964]57#define KA2PA(x) (((uintptr_t) (x)) - UINT64_C(0xffff800000000000))
58#define PA2KA(x) (((uintptr_t) (x)) + UINT64_C(0xffff800000000000))
[b3f8fb7]59
[a1f60f3]60#else /* __ASM__ */
61
62#define KA2PA(x) ((x) - 0xffff800000000000)
63#define PA2KA(x) ((x) + 0xffff800000000000)
64
65#endif /* __ASM__ */
[8fc0d455]66
[c03ee1c]67/* Number of entries in each level. */
[a1f60f3]68#define PTL0_ENTRIES_ARCH 512
69#define PTL1_ENTRIES_ARCH 512
70#define PTL2_ENTRIES_ARCH 512
71#define PTL3_ENTRIES_ARCH 512
[ecbdc724]72
[c03ee1c]73/* Page table sizes for each level. */
[a1f60f3]74#define PTL0_SIZE_ARCH ONE_FRAME
75#define PTL1_SIZE_ARCH ONE_FRAME
76#define PTL2_SIZE_ARCH ONE_FRAME
77#define PTL3_SIZE_ARCH ONE_FRAME
[c03ee1c]78
79/* Macros calculating indices into page tables in each level. */
[dc0b964]80#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 39) & 0x1ffU)
81#define PTL1_INDEX_ARCH(vaddr) (((vaddr) >> 30) & 0x1ffU)
82#define PTL2_INDEX_ARCH(vaddr) (((vaddr) >> 21) & 0x1ffU)
83#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x1ffU)
[c03ee1c]84
85/* Get PTE address accessors for each level. */
86#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
87 ((pte_t *) ((((uint64_t) ((pte_t *) (ptl0))[(i)].addr_12_31) << 12) | \
88 (((uint64_t) ((pte_t *) (ptl0))[(i)].addr_32_51) << 32)))
89#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
90 ((pte_t *) ((((uint64_t) ((pte_t *) (ptl1))[(i)].addr_12_31) << 12) | \
91 (((uint64_t) ((pte_t *) (ptl1))[(i)].addr_32_51) << 32)))
92#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
93 ((pte_t *) ((((uint64_t) ((pte_t *) (ptl2))[(i)].addr_12_31) << 12) | \
94 (((uint64_t) ((pte_t *) (ptl2))[(i)].addr_32_51) << 32)))
95#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
96 ((uintptr_t *) \
97 ((((uint64_t) ((pte_t *) (ptl3))[(i)].addr_12_31) << 12) | \
98 (((uint64_t) ((pte_t *) (ptl3))[(i)].addr_32_51) << 32)))
99
100/* Set PTE address accessors for each level. */
101#define SET_PTL0_ADDRESS_ARCH(ptl0) \
102 (write_cr3((uintptr_t) (ptl0)))
103#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
[98000fb]104 set_pt_addr((pte_t *) (ptl0), (size_t) (i), a)
[c03ee1c]105#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) \
[98000fb]106 set_pt_addr((pte_t *) (ptl1), (size_t) (i), a)
[c03ee1c]107#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) \
[98000fb]108 set_pt_addr((pte_t *) (ptl2), (size_t) (i), a)
[c03ee1c]109#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
[98000fb]110 set_pt_addr((pte_t *) (ptl3), (size_t) (i), a)
[c03ee1c]111
112/* Get PTE flags accessors for each level. */
113#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
[98000fb]114 get_pt_flags((pte_t *) (ptl0), (size_t) (i))
[c03ee1c]115#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
[98000fb]116 get_pt_flags((pte_t *) (ptl1), (size_t) (i))
[c03ee1c]117#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
[98000fb]118 get_pt_flags((pte_t *) (ptl2), (size_t) (i))
[c03ee1c]119#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
[98000fb]120 get_pt_flags((pte_t *) (ptl3), (size_t) (i))
[c03ee1c]121
122/* Set PTE flags accessors for each level. */
123#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
[98000fb]124 set_pt_flags((pte_t *) (ptl0), (size_t) (i), (x))
[c03ee1c]125#define SET_PTL2_FLAGS_ARCH(ptl1, i, x) \
[98000fb]126 set_pt_flags((pte_t *) (ptl1), (size_t) (i), (x))
[c03ee1c]127#define SET_PTL3_FLAGS_ARCH(ptl2, i, x) \
[98000fb]128 set_pt_flags((pte_t *) (ptl2), (size_t) (i), (x))
[c03ee1c]129#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
[98000fb]130 set_pt_flags((pte_t *) (ptl3), (size_t) (i), (x))
[c03ee1c]131
132/* Macros for querying the last-level PTE entries. */
133#define PTE_VALID_ARCH(p) \
134 (*((uint64_t *) (p)) != 0)
135#define PTE_PRESENT_ARCH(p) \
136 ((p)->present != 0)
137#define PTE_GET_FRAME_ARCH(p) \
138 ((((uintptr_t) (p)->addr_12_31) << 12) | \
139 ((uintptr_t) (p)->addr_32_51 << 32))
140#define PTE_WRITABLE_ARCH(p) \
141 ((p)->writeable != 0)
142#define PTE_EXECUTABLE_ARCH(p) \
143 ((p)->no_execute == 0)
[ecbdc724]144
[8fc0d455]145#ifndef __ASM__
[db3341e]146
[a1f60f3]147#include <mm/mm.h>
148#include <arch/interrupt.h>
149#include <typedefs.h>
150
[567807b1]151/* Page fault error codes. */
152
[c03ee1c]153/** When bit on this position is 0, the page fault was caused by a not-present
154 * page.
155 */
[a1f60f3]156#define PFERR_CODE_P (1 << 0)
[567807b1]157
158/** When bit on this position is 1, the page fault was caused by a write. */
[a1f60f3]159#define PFERR_CODE_RW (1 << 1)
[567807b1]160
161/** When bit on this position is 1, the page fault was caused in user mode. */
[a1f60f3]162#define PFERR_CODE_US (1 << 2)
[567807b1]163
164/** When bit on this position is 1, a reserved bit was set in page directory. */
[a1f60f3]165#define PFERR_CODE_RSVD (1 << 3)
[567807b1]166
[c03ee1c]167/** When bit on this position os 1, the page fault was caused during instruction
168 * fecth.
169 */
[a1f60f3]170#define PFERR_CODE_ID (1 << 4)
[567807b1]171
[33be9ac]172/** Page Table Entry. */
173typedef struct {
[a1f60f3]174 unsigned int present : 1;
175 unsigned int writeable : 1;
176 unsigned int uaccessible : 1;
177 unsigned int page_write_through : 1;
178 unsigned int page_cache_disable : 1;
179 unsigned int accessed : 1;
180 unsigned int dirty : 1;
181 unsigned int unused: 1;
182 unsigned int global : 1;
183 unsigned int soft_valid : 1; /**< Valid content even if present bit is cleared. */
184 unsigned int avl : 2;
185 unsigned int addr_12_31 : 30;
186 unsigned int addr_32_51 : 21;
187 unsigned int no_execute : 1;
[33be9ac]188} __attribute__ ((packed)) pte_t;
189
[7a0359b]190NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
[db3341e]191{
192 pte_t *p = &pt[i];
193
[c03ee1c]194 return ((!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT |
195 (!p->present) << PAGE_PRESENT_SHIFT |
196 p->uaccessible << PAGE_USER_SHIFT |
197 1 << PAGE_READ_SHIFT |
198 p->writeable << PAGE_WRITE_SHIFT |
199 (!p->no_execute) << PAGE_EXEC_SHIFT |
200 p->global << PAGE_GLOBAL_SHIFT);
[db3341e]201}
202
[7a0359b]203NO_TRACE static inline void set_pt_addr(pte_t *pt, size_t i, uintptr_t a)
[db3341e]204{
205 pte_t *p = &pt[i];
[a1f60f3]206
[dc0b964]207 p->addr_12_31 = (a >> 12) & UINT32_C(0xfffff);
[db3341e]208 p->addr_32_51 = a >> 32;
209}
210
[7a0359b]211NO_TRACE static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
[db3341e]212{
213 pte_t *p = &pt[i];
214
215 p->page_cache_disable = !(flags & PAGE_CACHEABLE);
216 p->present = !(flags & PAGE_NOT_PRESENT);
217 p->uaccessible = (flags & PAGE_USER) != 0;
218 p->writeable = (flags & PAGE_WRITE) != 0;
219 p->no_execute = (flags & PAGE_EXEC) == 0;
[bfb87df]220 p->global = (flags & PAGE_GLOBAL) != 0;
[0882a9a]221
222 /*
223 * Ensure that there is at least one bit set even if the present bit is cleared.
224 */
225 p->soft_valid = 1;
[db3341e]226}
227
[1141c1a]228extern void page_arch_init(void);
[214ec25c]229extern void page_fault(unsigned int, istate_t *);
[1141c1a]230
[d1f8a87]231#endif /* __ASM__ */
232
233#endif /* KERNEL */
[1141c1a]234
235#endif
[b45c443]236
[7f1c620]237/** @}
[b45c443]238 */
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