source: mainline/kernel.config@ 2f7342d

## General configuration directives

# Architecture
@ "ia32" Intel IA-32
@ "amd64" AMD64/Intel EM64T
@ "ia64" Intel IA-64
@ "mips32" MIPS 32-bit
@ "ppc32" PowerPC 32-bit
@ "sparc64" Sun UltraSPARC
! ARCH (choice)

# IA32 Compiler
@ "cross" Cross-compiler
@ "native" Native
! [ARCH=ia32] IA32_COMPILER (choice)
% [ARCH=ia32] SAVEAS IA32_COMPILER COMPILER

# AMD64 Compiler
@ "cross" Cross-compiler
@ "native" Native
! [ARCH=amd64] AMD64_COMPILER (choice)
% [ARCH=amd64] SAVEAS AMD64_COMPILER COMPILER

# Compiler
@ "cross" Cross-compiler
@ "native" Native
! [(ARCH!=amd64)&(ARCH!=ia32)] OTHER_COMPILER (choice)
% [(ARCH!=amd64)&(ARCH!=ia32)] SAVEAS OTHER_COMPILER COMPILER


# CPU type
@ "pentium4" Pentium 4
@ "pentium3" Pentium 3
@ "athlon-xp" Athlon XP
@ "athlon-mp" Athlon MP
@ "prescott" Prescott
! [ARCH=ia32] IA32_CPU (choice)

# MIPS Machine Type
@ "msim" MSIM Simulator
@ "simics" Virtutech Simics simulator
@ "lgxemul" GXEmul Little Endian
@ "bgxemul" GXEmul Big Endian
@ "indy" SGI Indy
! [ARCH=mips32] MIPS_MACHINE (choice)

# Framebuffer support
! [(ARCH=mips32&MIPS_MACHINE=lgxemul)|(ARCH=mips32&MIPS_MACHINE=bgxemul)] CONFIG_FB (y/n)

# Support for SMP
! [ARCH=ia32|ARCH=amd64] CONFIG_SMP (y/n)

# Improved support for hyperthreading
! [(ARCH=ia32|ARCH=amd64)&CONFIG_SMP=y] CONFIG_HT (y/n)

# Simics BIOS AP boot fix
! [(ARCH=ia32|ARCH=amd64)&CONFIG_SMP=y] CONFIG_SIMICS_FIX (y/n)

# Lazy FPU context switching
! [(ARCH=mips32&MIPS_MACHINE!=msim&MIPS_MACHINE!=simics)|ARCH=amd64|ARCH=ia32] CONFIG_FPU_LAZY (y/n)

# Power off on halt
! [ARCH=ppc32] CONFIG_POWEROFF (y/n)

## Debugging configuration directives

# General debuging and assert checking
! CONFIG_DEBUG (y/n)

# Deadlock detection support for spinlocks
! [CONFIG_DEBUG=y&CONFIG_SMP=y] CONFIG_DEBUG_SPINLOCK (y/n)

## Run-time configuration directives

# Kernel test type
@ "" No test
@ "synch/rwlock1" Read write test 1
@ "synch/rwlock2" Read write test 2
@ "synch/rwlock3" Read write test 3
@ "synch/rwlock4" Read write test 4
@ "synch/rwlock5" Read write test 5
@ "synch/semaphore1" Semaphore test 1
@ "synch/semaphore2" Sempahore test 2
@ [ARCH=ia32|ARCH=amd64] "fpu/fpu1" Intel fpu test 1
@ [ARCH=ia32|ARCH=amd64] "fpu/sse1" Intel Sse test 1
@ [ARCH=mips32&MIPS_MACHINE!=msim&MIPS_MACHINE!=simics] "fpu/mips1" Mips FPU test 1
@ "print/print1" Printf test 1
@ "thread/thread1" Thread test 1
@ "mm/mapping1" Mapping test 1
@ "mm/falloc1" Frame Allocation test 1
@ "mm/falloc2" Frame Allocation test 2
@ "mm/slab1" SLAB test1 - No CPU-cache
@ "mm/slab2" SLAB test2 - SMP CPU cache
@ "fault/fault1" Write to NULL (maybe page fault)
@ [ARCH=ia64] "mm/purge1" Itanium TLB purge test
@ [ARCH=mips32] "debug/mips1" Mips breakpoint-debug test 
! CONFIG_TEST (choice)