| 1 | ## General configuration directives
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| 2 |
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| 3 | # Architecture
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| 4 | @ "ia32" Intel IA-32
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| 5 | @ "amd64" AMD64/Intel EM64T
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| 6 | @ "ia64" Intel IA-64
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| 7 | @ "mips32" MIPS 32-bit
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| 8 | @ "ppc32" PowerPC 32-bit
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| 9 | @ "sparc64" Sun UltraSPARC
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| 10 | ! ARCH (choice)
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| 11 |
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| 12 | # IA32 Compiler
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| 13 | @ "cross" Cross-compiler
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| 14 | @ "native" Native
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| 15 | ! [ARCH=ia32] IA32_COMPILER (choice)
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| 16 | % [ARCH=ia32] SAVEAS IA32_COMPILER COMPILER
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| 17 |
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| 18 | # AMD64 Compiler
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| 19 | @ "cross" Cross-compiler
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| 20 | @ "native" Native
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| 21 | ! [ARCH=amd64] AMD64_COMPILER (choice)
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| 22 | % [ARCH=amd64] SAVEAS AMD64_COMPILER COMPILER
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| 23 |
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| 24 | # Compiler
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| 25 | @ "cross" Cross-compiler
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| 26 | @ "native" Native
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| 27 | ! [(ARCH!=amd64)&(ARCH!=ia32)] OTHER_COMPILER (choice)
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| 28 | % [(ARCH!=amd64)&(ARCH!=ia32)] SAVEAS OTHER_COMPILER COMPILER
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| 29 |
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| 30 |
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| 31 | # CPU type
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| 32 | @ "pentium4" Pentium 4
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| 33 | @ "pentium3" Pentium 3
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| 34 | @ "athlon-xp" Athlon XP
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| 35 | @ "athlon-mp" Athlon MP
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| 36 | @ "prescott" Prescott
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| 37 | ! [ARCH=ia32] IA32_CPU (choice)
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| 38 |
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| 39 | # MIPS Machine Type
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| 40 | @ "msim" MSIM Simulator
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| 41 | @ "simics" Virtutech Simics simulator
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| 42 | @ "lgxemul" GXEmul Little Endian
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| 43 | @ "bgxemul" GXEmul Big Endian
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| 44 | @ "indy" SGI Indy
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| 45 | ! [ARCH=mips32] MIPS_MACHINE (choice)
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| 46 |
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| 47 | # Framebuffer support
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| 48 | ! [(ARCH=mips32&MIPS_MACHINE=lgxemul)|(ARCH=mips32&MIPS_MACHINE=bgxemul)] CONFIG_FB (y/n)
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| 49 |
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| 50 | # Support for SMP
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| 51 | ! [ARCH=ia32|ARCH=amd64] CONFIG_SMP (y/n)
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| 52 |
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| 53 | # Improved support for hyperthreading
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| 54 | ! [(ARCH=ia32|ARCH=amd64)&CONFIG_SMP=y] CONFIG_HT (y/n)
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| 55 |
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| 56 | # Simics BIOS AP boot fix
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| 57 | ! [(ARCH=ia32|ARCH=amd64)&CONFIG_SMP=y] CONFIG_SIMICS_FIX (y/n)
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| 58 |
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| 59 | # Lazy FPU context switching
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| 60 | ! [(ARCH=mips32&MIPS_MACHINE!=msim&MIPS_MACHINE!=simics)|ARCH=amd64|ARCH=ia32] CONFIG_FPU_LAZY (y/n)
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| 61 |
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| 62 | # Power off on halt
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| 63 | ! [ARCH=ppc32] CONFIG_POWEROFF (y/n)
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| 64 |
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| 65 | ## Debugging configuration directives
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| 66 |
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| 67 | # General debuging and assert checking
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| 68 | ! CONFIG_DEBUG (y/n)
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| 69 |
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| 70 | # Deadlock detection support for spinlocks
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| 71 | ! [CONFIG_DEBUG=y&CONFIG_SMP=y] CONFIG_DEBUG_SPINLOCK (y/n)
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| 72 |
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| 73 | ## Run-time configuration directives
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| 74 |
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| 75 | # Kernel test type
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| 76 | @ "" No test
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| 77 | @ "synch/rwlock1" Read write test 1
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| 78 | @ "synch/rwlock2" Read write test 2
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| 79 | @ "synch/rwlock3" Read write test 3
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| 80 | @ "synch/rwlock4" Read write test 4
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| 81 | @ "synch/rwlock5" Read write test 5
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| 82 | @ "synch/semaphore1" Semaphore test 1
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| 83 | @ "synch/semaphore2" Sempahore test 2
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| 84 | @ [ARCH=ia32|ARCH=amd64] "fpu/fpu1" Intel fpu test 1
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| 85 | @ [ARCH=ia32|ARCH=amd64] "fpu/sse1" Intel Sse test 1
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| 86 | @ [ARCH=mips32&MIPS_MACHINE!=msim&MIPS_MACHINE!=simics] "fpu/mips1" Mips FPU test 1
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| 87 | @ "print/print1" Printf test 1
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| 88 | @ "thread/thread1" Thread test 1
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| 89 | @ "mm/mapping1" Mapping test 1
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| 90 | @ "mm/falloc1" Frame Allocation test 1
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| 91 | @ "mm/falloc2" Frame Allocation test 2
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| 92 | @ "mm/slab1" SLAB test1 - No CPU-cache
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| 93 | @ "mm/slab2" SLAB test2 - SMP CPU cache
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| 94 | @ "fault/fault1" Write to NULL (maybe page fault)
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| 95 | @ [ARCH=ia64] "mm/purge1" Itanium TLB purge test
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| 96 | @ [ARCH=mips32] "debug/mips1" Mips breakpoint-debug test
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| 97 | ! CONFIG_TEST (choice)
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