source: mainline/boot/arch/ppc32/src/asm.S@ c7fbb90

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since c7fbb90 was a2da43c, checked in by Jiri Svoboda <jiri@…>, 15 years ago

memcpy assembly blobs in boot stage are not needed. Replace them all with a simple C function.
  • Property mode set to 100644
File size: 6.0 KB
RevLine 
[5eb84ab]1#
[df4ed85]2# Copyright (c) 2006 Martin Decky
[5eb84ab]3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions
7# are met:
8#
9# - Redistributions of source code must retain the above copyright
10# notice, this list of conditions and the following disclaimer.
11# - Redistributions in binary form must reproduce the above copyright
12# notice, this list of conditions and the following disclaimer in the
13# documentation and/or other materials provided with the distribution.
14# - The name of the author may not be used to endorse or promote products
15# derived from this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28
[4872160]29#include <arch/arch.h>
30#include <arch/regname.h>
[5eb84ab]31
[7b187ef]32.macro SMC_COHERENCY addr
[34259b9]33 dcbst 0, \addr
34 sync
35 icbi 0, \addr
[7b187ef]36 sync
[34259b9]37 isync
38.endm
39
[7b187ef]40.macro FLUSH_DCACHE addr
41 dcbst 0, \addr
42 sync
43 isync
44.endm
45
46.macro TLB_FLUSH reg
[e731b0d]47 li \reg, 0
48 sync
49
50 .rept 64
51 tlbie \reg
52 addi \reg, \reg, 0x1000
53 .endr
54
55 eieio
56 tlbsync
57 sync
[7b187ef]58.endm
59
[4872160]60.global start
[01cb210]61.global halt
[5eb84ab]62.global jump_to_kernel
[4872160]63.global real_mode
64
65.section BOOTSTRAP, "ax"
66
67start:
68 lis r4, ofw_cif@ha
69 addi r4, r4, ofw_cif@l
70 stw r5, 0(r4)
71
72 bl ofw_init
73 b bootstrap
74
75.text
[5eb84ab]76
[01cb210]77halt:
78 b halt
[bcc223b2]79
[5eb84ab]80jump_to_kernel:
[1fbe8da2]81
[4872160]82 # arguments:
83 # r3 = bootinfo (physical address)
84 # r4 = translate table (physical address)
85 # r5 = pages to translate
86 # r6 = real mode meeting point (physical address)
[1fbe8da2]87
[ab4ac14]88 # disable interrupts
89
90 mfmsr r31
91 rlwinm r31, r31, 0, 17, 15
92 mtmsr r31
93
[4872160]94 # set real mode meeting point physical address
[ab4ac14]95
[4872160]96 mtspr srr0, r6
[1fbe8da2]97
[4872160]98 # jump to real_mode
[1fbe8da2]99
[01cb210]100 mfmsr r31
101 lis r30, ~0@h
[4520dc02]102 ori r30, r30, ~(msr_ir | msr_dr | msr_ee)@l
[01cb210]103 and r31, r31, r30
104 mtspr srr1, r31
[89343aac]105
106 sync
107 isync
[1fbe8da2]108 rfi
109
[02e7700]110.section REALMODE, "ax"
[e731b0d]111
[01cb210]112.align PAGE_WIDTH
[1fbe8da2]113real_mode:
[bbeb5e4]114
[4872160]115 # arguments:
116 # r3 = bootinfo (physical address)
117 # r4 = translate table (physical address)
118 # r5 = pages to translate
119
120 # move the images of components to the proper
121 # location using the translate table
[01cb210]122
[1f330de]123 li r31, PAGE_SIZE >> 2
[01cb210]124 li r30, 0
125
126 page_copy:
127
[4872160]128 cmpwi r5, 0
[01cb210]129 beq copy_end
130
131 mtctr r31
[4872160]132 lwz r29, 0(r4)
[01cb210]133
134 copy_loop:
135
136 lwz r28, 0(r29)
137 stw r28, 0(r30)
138
[7b187ef]139 SMC_COHERENCY r30
[34259b9]140
[01cb210]141 addi r29, r29, 4
142 addi r30, r30, 4
143
144 bdnz copy_loop
[4872160]145
146 addi r4, r4, 4
147 subi r5, r5, 1
[01cb210]148 b page_copy
149
150 copy_end:
[1f330de]151
[02e7700]152 # initially fill segment registers
[2988616b]153
[543c31f]154 li r31, 0
[2988616b]155
156 li r29, 8
157 mtctr r29
[bab785fe]158 li r30, 0 # ASID 0 (VSIDs 0 .. 7)
[34259b9]159
[2988616b]160 seg_fill_uspace:
[1fbe8da2]161
[543c31f]162 mtsrin r30, r31
[2988616b]163 addi r30, r30, 1
[543c31f]164 addis r31, r31, 0x1000 # move to next SR
165
[2988616b]166 bdnz seg_fill_uspace
167
168 li r29, 8
169 mtctr r29
[bab785fe]170 lis r30, 0x4000 # priviledged access only
171 ori r30, r30, 8 # ASID 0 (VSIDs 8 .. 15)
[2988616b]172
173 seg_fill_kernel:
174
175 mtsrin r30, r31
176 addi r30, r30, 1
177 addis r31, r31, 0x1000 # move to next SR
178
179 bdnz seg_fill_kernel
[1f330de]180
181 # invalidate block address translation registers
182
[c3b5cdf]183 li r30, 0
184
[1f330de]185 mtspr ibat0u, r30
186 mtspr ibat0l, r30
187
188 mtspr ibat1u, r30
189 mtspr ibat1l, r30
190
191 mtspr ibat2u, r30
192 mtspr ibat2l, r30
193
194 mtspr ibat3u, r30
195 mtspr ibat3l, r30
196
197 mtspr dbat0u, r30
198 mtspr dbat0l, r30
199
200 mtspr dbat1u, r30
201 mtspr dbat1l, r30
202
203 mtspr dbat2u, r30
204 mtspr dbat2l, r30
205
206 mtspr dbat3u, r30
207 mtspr dbat3l, r30
[1fbe8da2]208
[60316bd]209 # create empty Page Hash Table
210 # on top of memory, size 64 KB
[c04bdb4]211
[4872160]212 lwz r31, 4(r3) # r31 = memory size
[c04bdb4]213
[60316bd]214 lis r30, 65536@h
215 ori r30, r30, 65536@l # r30 = 65536
216
217 subi r29, r30, 1 # r29 = 65535
218
219 sub r31, r31, r30
220 andc r31, r31, r29 # pht = ALIGN_DOWN(memory_size - 65536, 65536)
221
222 mtsdr1 r31
223
224 li r29, 2
225 srw r30, r30, r29 # r30 = 16384
[2988616b]226 li r29, 0
227
228 pht_clear:
229
[bab785fe]230 # write zeroes
231
[2988616b]232 stw r29, 0(r31)
[7b187ef]233 FLUSH_DCACHE r31
[2988616b]234
235 addi r31, r31, 4
236 subi r30, r30, 4
237
238 cmpwi r30, 0
239 beq clear_end
240
241 bdnz pht_clear
242
243 clear_end:
244
245#ifdef CONFIG_BAT
246
[bab785fe]247 # create BAT identity mapping
248
[4872160]249 lwz r31, 4(r3) # r31 = memory size
[bab785fe]250
251 lis r29, 0x0002
252 cmpw r31, r29
253 blt no_bat # less than 128 KB -> no BAT
254
255 li r29, 18
256 srw r31, r31, r29 # r31 = total >> 18
[1f330de]257
[bab785fe]258 # create Block Length mask by replicating
259 # the leading logical one 14 times
260
261 li r29, 14
262 mtctr r31
263 li r29, 1
264
265 bat_mask:
266 srw r30, r31, r29 # r30 = mask >> 1
267 or r31, r31, r30 # mask = mask | r30
268
269 bdnz bat_mask
270
271 andi. r31, r31, 0x07ff # mask = mask & 0x07ff (BAT can map up to 256 MB)
272
273 li r29, 2
274 slw r31, r31, r29 # mask = mask << 2
275 ori r31, r31, 0x0002 # mask = mask | 0x0002 (priviledged access only)
276
277 lis r29, 0x8000
278 or r29, r29, r31
[1f330de]279
280 lis r30, 0x0000
281 ori r30, r30, 0x0002
282
[bab785fe]283 mtspr ibat0u, r29
[1f330de]284 mtspr ibat0l, r30
285
[bab785fe]286 mtspr dbat0u, r29
[1f330de]287 mtspr dbat0l, r30
[bab785fe]288
289 no_bat:
[1f330de]290
[f3776a3]291#endif
[bbeb5e4]292
[7b187ef]293 # flush TLB
294
295 TLB_FLUSH r31
296
[01cb210]297 # start the kernel
[1fbe8da2]298 #
[e731b0d]299 # pc = PA2KA(BOOT_OFFSET)
[4872160]300 # r3 = bootinfo (physical address)
[e731b0d]301 # sprg0 = BOOT_OFFSET
[2988616b]302 # sprg3 = physical memory size
[4872160]303 # sp = 0 (enforces the usage of sprg0 as exception stack)
[01cb210]304
[e731b0d]305 lis r31, PA2KA(BOOT_OFFSET)@ha
306 addi r31, r31, PA2KA(BOOT_OFFSET)@l
[01cb210]307 mtspr srr0, r31
[1fbe8da2]308
[e731b0d]309 lis r31, BOOT_OFFSET@ha
310 addi r31, r31, BOOT_OFFSET@l
[2988616b]311 mtsprg0 r31
312
[4872160]313 # bootinfo starts with a 64 bit integer containing
314 # the physical memory size, get the lower 4 bytes
315
316 lwz r31, 4(r3)
[2988616b]317 mtsprg3 r31
318
319 li sp, 0
320
[01cb210]321 mfmsr r31
322 ori r31, r31, (msr_ir | msr_dr)@l
323 mtspr srr1, r31
[1fbe8da2]324
[38fe9d0]325 sync
326 isync
[1fbe8da2]327 rfi
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