source: mainline/boot/arch/ppc32/src/asm.S@ 46757a6

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 46757a6 was 4872160, checked in by Martin Decky <martin@…>, 16 years ago

new boot infrastructure

  • more code and metadata unification
  • import of up-to-date implementations from the kernel
  • the boot loaders should behave more similarly on all platforms
  • support for deflate compressed (LZ77) boot components
    • this again allows feasible boot images to be created on mips32
  • IA64 is still not booting
    • the broken forked GNU EFI library has been removed, a replacement of the functionality is on its way
  • Property mode set to 100644
File size: 6.6 KB
Line 
1#
2# Copyright (c) 2006 Martin Decky
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions
7# are met:
8#
9# - Redistributions of source code must retain the above copyright
10# notice, this list of conditions and the following disclaimer.
11# - Redistributions in binary form must reproduce the above copyright
12# notice, this list of conditions and the following disclaimer in the
13# documentation and/or other materials provided with the distribution.
14# - The name of the author may not be used to endorse or promote products
15# derived from this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28
29#include <arch/arch.h>
30#include <arch/regname.h>
31
32.macro SMC_COHERENCY addr
33 dcbst 0, \addr
34 sync
35 icbi 0, \addr
36 sync
37 isync
38.endm
39
40.macro FLUSH_DCACHE addr
41 dcbst 0, \addr
42 sync
43 isync
44.endm
45
46.macro TLB_FLUSH reg
47 li \reg, 0
48 sync
49
50 .rept 64
51 tlbie \reg
52 addi \reg, \reg, 0x1000
53 .endr
54
55 eieio
56 tlbsync
57 sync
58.endm
59
60.global start
61.global halt
62.global memcpy
63.global jump_to_kernel
64.global real_mode
65
66.section BOOTSTRAP, "ax"
67
68start:
69 lis r4, ofw_cif@ha
70 addi r4, r4, ofw_cif@l
71 stw r5, 0(r4)
72
73 bl ofw_init
74 b bootstrap
75
76.text
77
78halt:
79 b halt
80
81memcpy:
82 srwi. r7, r5, 3
83 addi r6, r3, -4
84 addi r4, r4, -4
85 beq 2f
86
87 andi. r0, r6, 3
88 mtctr r7
89 bne 5f
90
91 1:
92 lwz r7, 4(r4)
93 lwzu r8, 8(r4)
94 stw r7, 4(r6)
95 stwu r8, 8(r6)
96 bdnz 1b
97
98 andi. r5, r5, 7
99
100 2:
101 cmplwi 0, r5, 4
102 blt 3f
103
104 lwzu r0, 4(r4)
105 addi r5, r5, -4
106 stwu r0, 4(r6)
107
108 3:
109 cmpwi 0, r5, 0
110 beqlr
111 mtctr r5
112 addi r4, r4, 3
113 addi r6, r6, 3
114
115 4:
116 lbzu r0, 1(r4)
117 stbu r0, 1(r6)
118 bdnz 4b
119 blr
120
121 5:
122 subfic r0, r0, 4
123 mtctr r0
124
125 6:
126 lbz r7, 4(r4)
127 addi r4, r4, 1
128 stb r7, 4(r6)
129 addi r6, r6, 1
130 bdnz 6b
131 subf r5, r0, r5
132 rlwinm. r7, r5, 32-3, 3, 31
133 beq 2b
134 mtctr r7
135 b 1b
136
137jump_to_kernel:
138
139 # arguments:
140 # r3 = bootinfo (physical address)
141 # r4 = translate table (physical address)
142 # r5 = pages to translate
143 # r6 = real mode meeting point (physical address)
144
145 # disable interrupts
146
147 mfmsr r31
148 rlwinm r31, r31, 0, 17, 15
149 mtmsr r31
150
151 # set real mode meeting point physical address
152
153 mtspr srr0, r6
154
155 # jump to real_mode
156
157 mfmsr r31
158 lis r30, ~0@h
159 ori r30, r30, ~(msr_ir | msr_dr | msr_ee)@l
160 and r31, r31, r30
161 mtspr srr1, r31
162
163 sync
164 isync
165 rfi
166
167.section REALMODE, "ax"
168
169.align PAGE_WIDTH
170real_mode:
171
172 # arguments:
173 # r3 = bootinfo (physical address)
174 # r4 = translate table (physical address)
175 # r5 = pages to translate
176
177 # move the images of components to the proper
178 # location using the translate table
179
180 li r31, PAGE_SIZE >> 2
181 li r30, 0
182
183 page_copy:
184
185 cmpwi r5, 0
186 beq copy_end
187
188 mtctr r31
189 lwz r29, 0(r4)
190
191 copy_loop:
192
193 lwz r28, 0(r29)
194 stw r28, 0(r30)
195
196 SMC_COHERENCY r30
197
198 addi r29, r29, 4
199 addi r30, r30, 4
200
201 bdnz copy_loop
202
203 addi r4, r4, 4
204 subi r5, r5, 1
205 b page_copy
206
207 copy_end:
208
209 # initially fill segment registers
210
211 li r31, 0
212
213 li r29, 8
214 mtctr r29
215 li r30, 0 # ASID 0 (VSIDs 0 .. 7)
216
217 seg_fill_uspace:
218
219 mtsrin r30, r31
220 addi r30, r30, 1
221 addis r31, r31, 0x1000 # move to next SR
222
223 bdnz seg_fill_uspace
224
225 li r29, 8
226 mtctr r29
227 lis r30, 0x4000 # priviledged access only
228 ori r30, r30, 8 # ASID 0 (VSIDs 8 .. 15)
229
230 seg_fill_kernel:
231
232 mtsrin r30, r31
233 addi r30, r30, 1
234 addis r31, r31, 0x1000 # move to next SR
235
236 bdnz seg_fill_kernel
237
238 # invalidate block address translation registers
239
240 li r30, 0
241
242 mtspr ibat0u, r30
243 mtspr ibat0l, r30
244
245 mtspr ibat1u, r30
246 mtspr ibat1l, r30
247
248 mtspr ibat2u, r30
249 mtspr ibat2l, r30
250
251 mtspr ibat3u, r30
252 mtspr ibat3l, r30
253
254 mtspr dbat0u, r30
255 mtspr dbat0l, r30
256
257 mtspr dbat1u, r30
258 mtspr dbat1l, r30
259
260 mtspr dbat2u, r30
261 mtspr dbat2l, r30
262
263 mtspr dbat3u, r30
264 mtspr dbat3l, r30
265
266 # create empty Page Hash Table
267 # on top of memory, size 64 KB
268
269 lwz r31, 4(r3) # r31 = memory size
270
271 lis r30, 65536@h
272 ori r30, r30, 65536@l # r30 = 65536
273
274 subi r29, r30, 1 # r29 = 65535
275
276 sub r31, r31, r30
277 andc r31, r31, r29 # pht = ALIGN_DOWN(memory_size - 65536, 65536)
278
279 mtsdr1 r31
280
281 li r29, 2
282 srw r30, r30, r29 # r30 = 16384
283 li r29, 0
284
285 pht_clear:
286
287 # write zeroes
288
289 stw r29, 0(r31)
290 FLUSH_DCACHE r31
291
292 addi r31, r31, 4
293 subi r30, r30, 4
294
295 cmpwi r30, 0
296 beq clear_end
297
298 bdnz pht_clear
299
300 clear_end:
301
302#ifdef CONFIG_BAT
303
304 # create BAT identity mapping
305
306 lwz r31, 4(r3) # r31 = memory size
307
308 lis r29, 0x0002
309 cmpw r31, r29
310 blt no_bat # less than 128 KB -> no BAT
311
312 li r29, 18
313 srw r31, r31, r29 # r31 = total >> 18
314
315 # create Block Length mask by replicating
316 # the leading logical one 14 times
317
318 li r29, 14
319 mtctr r31
320 li r29, 1
321
322 bat_mask:
323 srw r30, r31, r29 # r30 = mask >> 1
324 or r31, r31, r30 # mask = mask | r30
325
326 bdnz bat_mask
327
328 andi. r31, r31, 0x07ff # mask = mask & 0x07ff (BAT can map up to 256 MB)
329
330 li r29, 2
331 slw r31, r31, r29 # mask = mask << 2
332 ori r31, r31, 0x0002 # mask = mask | 0x0002 (priviledged access only)
333
334 lis r29, 0x8000
335 or r29, r29, r31
336
337 lis r30, 0x0000
338 ori r30, r30, 0x0002
339
340 mtspr ibat0u, r29
341 mtspr ibat0l, r30
342
343 mtspr dbat0u, r29
344 mtspr dbat0l, r30
345
346 no_bat:
347
348#endif
349
350 # flush TLB
351
352 TLB_FLUSH r31
353
354 # start the kernel
355 #
356 # pc = PA2KA(BOOT_OFFSET)
357 # r3 = bootinfo (physical address)
358 # sprg0 = BOOT_OFFSET
359 # sprg3 = physical memory size
360 # sp = 0 (enforces the usage of sprg0 as exception stack)
361
362 lis r31, PA2KA(BOOT_OFFSET)@ha
363 addi r31, r31, PA2KA(BOOT_OFFSET)@l
364 mtspr srr0, r31
365
366 lis r31, BOOT_OFFSET@ha
367 addi r31, r31, BOOT_OFFSET@l
368 mtsprg0 r31
369
370 # bootinfo starts with a 64 bit integer containing
371 # the physical memory size, get the lower 4 bytes
372
373 lwz r31, 4(r3)
374 mtsprg3 r31
375
376 li sp, 0
377
378 mfmsr r31
379 ori r31, r31, (msr_ir | msr_dr)@l
380 mtspr srr1, r31
381
382 sync
383 isync
384 rfi
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