| [5eb84ab] | 1 | #
|
|---|
| [df4ed85] | 2 | # Copyright (c) 2006 Martin Decky
|
|---|
| [5eb84ab] | 3 | # All rights reserved.
|
|---|
| 4 | #
|
|---|
| 5 | # Redistribution and use in source and binary forms, with or without
|
|---|
| 6 | # modification, are permitted provided that the following conditions
|
|---|
| 7 | # are met:
|
|---|
| 8 | #
|
|---|
| 9 | # - Redistributions of source code must retain the above copyright
|
|---|
| 10 | # notice, this list of conditions and the following disclaimer.
|
|---|
| 11 | # - Redistributions in binary form must reproduce the above copyright
|
|---|
| 12 | # notice, this list of conditions and the following disclaimer in the
|
|---|
| 13 | # documentation and/or other materials provided with the distribution.
|
|---|
| 14 | # - The name of the author may not be used to endorse or promote products
|
|---|
| 15 | # derived from this software without specific prior written permission.
|
|---|
| 16 | #
|
|---|
| 17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
|---|
| 18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
|---|
| 19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|---|
| 20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|---|
| 21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|---|
| 22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|---|
| 23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|---|
| 24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|---|
| 25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
|---|
| 26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|---|
| 27 | #
|
|---|
| 28 |
|
|---|
| [4872160] | 29 | #include <arch/arch.h>
|
|---|
| 30 | #include <arch/regname.h>
|
|---|
| [5eb84ab] | 31 |
|
|---|
| [7b187ef] | 32 | .macro SMC_COHERENCY addr
|
|---|
| [34259b9] | 33 | dcbst 0, \addr
|
|---|
| 34 | sync
|
|---|
| 35 | icbi 0, \addr
|
|---|
| [7b187ef] | 36 | sync
|
|---|
| [34259b9] | 37 | isync
|
|---|
| 38 | .endm
|
|---|
| 39 |
|
|---|
| [7b187ef] | 40 | .macro FLUSH_DCACHE addr
|
|---|
| 41 | dcbst 0, \addr
|
|---|
| 42 | sync
|
|---|
| 43 | isync
|
|---|
| 44 | .endm
|
|---|
| 45 |
|
|---|
| 46 | .macro TLB_FLUSH reg
|
|---|
| [e731b0d] | 47 | li \reg, 0
|
|---|
| 48 | sync
|
|---|
| 49 |
|
|---|
| 50 | .rept 64
|
|---|
| 51 | tlbie \reg
|
|---|
| 52 | addi \reg, \reg, 0x1000
|
|---|
| 53 | .endr
|
|---|
| 54 |
|
|---|
| 55 | eieio
|
|---|
| 56 | tlbsync
|
|---|
| 57 | sync
|
|---|
| [7b187ef] | 58 | .endm
|
|---|
| 59 |
|
|---|
| [4872160] | 60 | .global start
|
|---|
| [01cb210] | 61 | .global halt
|
|---|
| [f941347] | 62 | .global memcpy
|
|---|
| [5eb84ab] | 63 | .global jump_to_kernel
|
|---|
| [4872160] | 64 | .global real_mode
|
|---|
| 65 |
|
|---|
| 66 | .section BOOTSTRAP, "ax"
|
|---|
| 67 |
|
|---|
| 68 | start:
|
|---|
| 69 | lis r4, ofw_cif@ha
|
|---|
| 70 | addi r4, r4, ofw_cif@l
|
|---|
| 71 | stw r5, 0(r4)
|
|---|
| 72 |
|
|---|
| 73 | bl ofw_init
|
|---|
| 74 | b bootstrap
|
|---|
| 75 |
|
|---|
| 76 | .text
|
|---|
| [5eb84ab] | 77 |
|
|---|
| [01cb210] | 78 | halt:
|
|---|
| 79 | b halt
|
|---|
| [bcc223b2] | 80 |
|
|---|
| [f941347] | 81 | memcpy:
|
|---|
| 82 | srwi. r7, r5, 3
|
|---|
| 83 | addi r6, r3, -4
|
|---|
| 84 | addi r4, r4, -4
|
|---|
| [e731b0d] | 85 | beq 2f
|
|---|
| [f941347] | 86 |
|
|---|
| 87 | andi. r0, r6, 3
|
|---|
| 88 | mtctr r7
|
|---|
| 89 | bne 5f
|
|---|
| 90 |
|
|---|
| 91 | 1:
|
|---|
| [e731b0d] | 92 | lwz r7, 4(r4)
|
|---|
| 93 | lwzu r8, 8(r4)
|
|---|
| 94 | stw r7, 4(r6)
|
|---|
| 95 | stwu r8, 8(r6)
|
|---|
| 96 | bdnz 1b
|
|---|
| 97 |
|
|---|
| 98 | andi. r5, r5, 7
|
|---|
| [f941347] | 99 |
|
|---|
| 100 | 2:
|
|---|
| [e731b0d] | 101 | cmplwi 0, r5, 4
|
|---|
| 102 | blt 3f
|
|---|
| 103 |
|
|---|
| 104 | lwzu r0, 4(r4)
|
|---|
| 105 | addi r5, r5, -4
|
|---|
| 106 | stwu r0, 4(r6)
|
|---|
| [f941347] | 107 |
|
|---|
| 108 | 3:
|
|---|
| [e731b0d] | 109 | cmpwi 0, r5, 0
|
|---|
| 110 | beqlr
|
|---|
| 111 | mtctr r5
|
|---|
| 112 | addi r4, r4, 3
|
|---|
| 113 | addi r6, r6, 3
|
|---|
| [f941347] | 114 |
|
|---|
| 115 | 4:
|
|---|
| [e731b0d] | 116 | lbzu r0, 1(r4)
|
|---|
| 117 | stbu r0, 1(r6)
|
|---|
| 118 | bdnz 4b
|
|---|
| 119 | blr
|
|---|
| [f941347] | 120 |
|
|---|
| 121 | 5:
|
|---|
| [e731b0d] | 122 | subfic r0, r0, 4
|
|---|
| 123 | mtctr r0
|
|---|
| [f941347] | 124 |
|
|---|
| 125 | 6:
|
|---|
| [e731b0d] | 126 | lbz r7, 4(r4)
|
|---|
| 127 | addi r4, r4, 1
|
|---|
| 128 | stb r7, 4(r6)
|
|---|
| 129 | addi r6, r6, 1
|
|---|
| 130 | bdnz 6b
|
|---|
| 131 | subf r5, r0, r5
|
|---|
| 132 | rlwinm. r7, r5, 32-3, 3, 31
|
|---|
| 133 | beq 2b
|
|---|
| 134 | mtctr r7
|
|---|
| 135 | b 1b
|
|---|
| [f941347] | 136 |
|
|---|
| [5eb84ab] | 137 | jump_to_kernel:
|
|---|
| [1fbe8da2] | 138 |
|
|---|
| [4872160] | 139 | # arguments:
|
|---|
| 140 | # r3 = bootinfo (physical address)
|
|---|
| 141 | # r4 = translate table (physical address)
|
|---|
| 142 | # r5 = pages to translate
|
|---|
| 143 | # r6 = real mode meeting point (physical address)
|
|---|
| [1fbe8da2] | 144 |
|
|---|
| [ab4ac14] | 145 | # disable interrupts
|
|---|
| 146 |
|
|---|
| 147 | mfmsr r31
|
|---|
| 148 | rlwinm r31, r31, 0, 17, 15
|
|---|
| 149 | mtmsr r31
|
|---|
| 150 |
|
|---|
| [4872160] | 151 | # set real mode meeting point physical address
|
|---|
| [ab4ac14] | 152 |
|
|---|
| [4872160] | 153 | mtspr srr0, r6
|
|---|
| [1fbe8da2] | 154 |
|
|---|
| [4872160] | 155 | # jump to real_mode
|
|---|
| [1fbe8da2] | 156 |
|
|---|
| [01cb210] | 157 | mfmsr r31
|
|---|
| 158 | lis r30, ~0@h
|
|---|
| [4520dc02] | 159 | ori r30, r30, ~(msr_ir | msr_dr | msr_ee)@l
|
|---|
| [01cb210] | 160 | and r31, r31, r30
|
|---|
| 161 | mtspr srr1, r31
|
|---|
| [89343aac] | 162 |
|
|---|
| 163 | sync
|
|---|
| 164 | isync
|
|---|
| [1fbe8da2] | 165 | rfi
|
|---|
| 166 |
|
|---|
| [02e7700] | 167 | .section REALMODE, "ax"
|
|---|
| [e731b0d] | 168 |
|
|---|
| [01cb210] | 169 | .align PAGE_WIDTH
|
|---|
| [1fbe8da2] | 170 | real_mode:
|
|---|
| [bbeb5e4] | 171 |
|
|---|
| [4872160] | 172 | # arguments:
|
|---|
| 173 | # r3 = bootinfo (physical address)
|
|---|
| 174 | # r4 = translate table (physical address)
|
|---|
| 175 | # r5 = pages to translate
|
|---|
| 176 |
|
|---|
| 177 | # move the images of components to the proper
|
|---|
| 178 | # location using the translate table
|
|---|
| [01cb210] | 179 |
|
|---|
| [1f330de] | 180 | li r31, PAGE_SIZE >> 2
|
|---|
| [01cb210] | 181 | li r30, 0
|
|---|
| 182 |
|
|---|
| 183 | page_copy:
|
|---|
| 184 |
|
|---|
| [4872160] | 185 | cmpwi r5, 0
|
|---|
| [01cb210] | 186 | beq copy_end
|
|---|
| 187 |
|
|---|
| 188 | mtctr r31
|
|---|
| [4872160] | 189 | lwz r29, 0(r4)
|
|---|
| [01cb210] | 190 |
|
|---|
| 191 | copy_loop:
|
|---|
| 192 |
|
|---|
| 193 | lwz r28, 0(r29)
|
|---|
| 194 | stw r28, 0(r30)
|
|---|
| 195 |
|
|---|
| [7b187ef] | 196 | SMC_COHERENCY r30
|
|---|
| [34259b9] | 197 |
|
|---|
| [01cb210] | 198 | addi r29, r29, 4
|
|---|
| 199 | addi r30, r30, 4
|
|---|
| 200 |
|
|---|
| 201 | bdnz copy_loop
|
|---|
| [4872160] | 202 |
|
|---|
| 203 | addi r4, r4, 4
|
|---|
| 204 | subi r5, r5, 1
|
|---|
| [01cb210] | 205 | b page_copy
|
|---|
| 206 |
|
|---|
| 207 | copy_end:
|
|---|
| [1f330de] | 208 |
|
|---|
| [02e7700] | 209 | # initially fill segment registers
|
|---|
| [2988616b] | 210 |
|
|---|
| [543c31f] | 211 | li r31, 0
|
|---|
| [2988616b] | 212 |
|
|---|
| 213 | li r29, 8
|
|---|
| 214 | mtctr r29
|
|---|
| [bab785fe] | 215 | li r30, 0 # ASID 0 (VSIDs 0 .. 7)
|
|---|
| [34259b9] | 216 |
|
|---|
| [2988616b] | 217 | seg_fill_uspace:
|
|---|
| [1fbe8da2] | 218 |
|
|---|
| [543c31f] | 219 | mtsrin r30, r31
|
|---|
| [2988616b] | 220 | addi r30, r30, 1
|
|---|
| [543c31f] | 221 | addis r31, r31, 0x1000 # move to next SR
|
|---|
| 222 |
|
|---|
| [2988616b] | 223 | bdnz seg_fill_uspace
|
|---|
| 224 |
|
|---|
| 225 | li r29, 8
|
|---|
| 226 | mtctr r29
|
|---|
| [bab785fe] | 227 | lis r30, 0x4000 # priviledged access only
|
|---|
| 228 | ori r30, r30, 8 # ASID 0 (VSIDs 8 .. 15)
|
|---|
| [2988616b] | 229 |
|
|---|
| 230 | seg_fill_kernel:
|
|---|
| 231 |
|
|---|
| 232 | mtsrin r30, r31
|
|---|
| 233 | addi r30, r30, 1
|
|---|
| 234 | addis r31, r31, 0x1000 # move to next SR
|
|---|
| 235 |
|
|---|
| 236 | bdnz seg_fill_kernel
|
|---|
| [1f330de] | 237 |
|
|---|
| 238 | # invalidate block address translation registers
|
|---|
| 239 |
|
|---|
| [c3b5cdf] | 240 | li r30, 0
|
|---|
| 241 |
|
|---|
| [1f330de] | 242 | mtspr ibat0u, r30
|
|---|
| 243 | mtspr ibat0l, r30
|
|---|
| 244 |
|
|---|
| 245 | mtspr ibat1u, r30
|
|---|
| 246 | mtspr ibat1l, r30
|
|---|
| 247 |
|
|---|
| 248 | mtspr ibat2u, r30
|
|---|
| 249 | mtspr ibat2l, r30
|
|---|
| 250 |
|
|---|
| 251 | mtspr ibat3u, r30
|
|---|
| 252 | mtspr ibat3l, r30
|
|---|
| 253 |
|
|---|
| 254 | mtspr dbat0u, r30
|
|---|
| 255 | mtspr dbat0l, r30
|
|---|
| 256 |
|
|---|
| 257 | mtspr dbat1u, r30
|
|---|
| 258 | mtspr dbat1l, r30
|
|---|
| 259 |
|
|---|
| 260 | mtspr dbat2u, r30
|
|---|
| 261 | mtspr dbat2l, r30
|
|---|
| 262 |
|
|---|
| 263 | mtspr dbat3u, r30
|
|---|
| 264 | mtspr dbat3l, r30
|
|---|
| [1fbe8da2] | 265 |
|
|---|
| [60316bd] | 266 | # create empty Page Hash Table
|
|---|
| 267 | # on top of memory, size 64 KB
|
|---|
| [c04bdb4] | 268 |
|
|---|
| [4872160] | 269 | lwz r31, 4(r3) # r31 = memory size
|
|---|
| [c04bdb4] | 270 |
|
|---|
| [60316bd] | 271 | lis r30, 65536@h
|
|---|
| 272 | ori r30, r30, 65536@l # r30 = 65536
|
|---|
| 273 |
|
|---|
| 274 | subi r29, r30, 1 # r29 = 65535
|
|---|
| 275 |
|
|---|
| 276 | sub r31, r31, r30
|
|---|
| 277 | andc r31, r31, r29 # pht = ALIGN_DOWN(memory_size - 65536, 65536)
|
|---|
| 278 |
|
|---|
| 279 | mtsdr1 r31
|
|---|
| 280 |
|
|---|
| 281 | li r29, 2
|
|---|
| 282 | srw r30, r30, r29 # r30 = 16384
|
|---|
| [2988616b] | 283 | li r29, 0
|
|---|
| 284 |
|
|---|
| 285 | pht_clear:
|
|---|
| 286 |
|
|---|
| [bab785fe] | 287 | # write zeroes
|
|---|
| 288 |
|
|---|
| [2988616b] | 289 | stw r29, 0(r31)
|
|---|
| [7b187ef] | 290 | FLUSH_DCACHE r31
|
|---|
| [2988616b] | 291 |
|
|---|
| 292 | addi r31, r31, 4
|
|---|
| 293 | subi r30, r30, 4
|
|---|
| 294 |
|
|---|
| 295 | cmpwi r30, 0
|
|---|
| 296 | beq clear_end
|
|---|
| 297 |
|
|---|
| 298 | bdnz pht_clear
|
|---|
| 299 |
|
|---|
| 300 | clear_end:
|
|---|
| 301 |
|
|---|
| 302 | #ifdef CONFIG_BAT
|
|---|
| 303 |
|
|---|
| [bab785fe] | 304 | # create BAT identity mapping
|
|---|
| 305 |
|
|---|
| [4872160] | 306 | lwz r31, 4(r3) # r31 = memory size
|
|---|
| [bab785fe] | 307 |
|
|---|
| 308 | lis r29, 0x0002
|
|---|
| 309 | cmpw r31, r29
|
|---|
| 310 | blt no_bat # less than 128 KB -> no BAT
|
|---|
| 311 |
|
|---|
| 312 | li r29, 18
|
|---|
| 313 | srw r31, r31, r29 # r31 = total >> 18
|
|---|
| [1f330de] | 314 |
|
|---|
| [bab785fe] | 315 | # create Block Length mask by replicating
|
|---|
| 316 | # the leading logical one 14 times
|
|---|
| 317 |
|
|---|
| 318 | li r29, 14
|
|---|
| 319 | mtctr r31
|
|---|
| 320 | li r29, 1
|
|---|
| 321 |
|
|---|
| 322 | bat_mask:
|
|---|
| 323 | srw r30, r31, r29 # r30 = mask >> 1
|
|---|
| 324 | or r31, r31, r30 # mask = mask | r30
|
|---|
| 325 |
|
|---|
| 326 | bdnz bat_mask
|
|---|
| 327 |
|
|---|
| 328 | andi. r31, r31, 0x07ff # mask = mask & 0x07ff (BAT can map up to 256 MB)
|
|---|
| 329 |
|
|---|
| 330 | li r29, 2
|
|---|
| 331 | slw r31, r31, r29 # mask = mask << 2
|
|---|
| 332 | ori r31, r31, 0x0002 # mask = mask | 0x0002 (priviledged access only)
|
|---|
| 333 |
|
|---|
| 334 | lis r29, 0x8000
|
|---|
| 335 | or r29, r29, r31
|
|---|
| [1f330de] | 336 |
|
|---|
| 337 | lis r30, 0x0000
|
|---|
| 338 | ori r30, r30, 0x0002
|
|---|
| 339 |
|
|---|
| [bab785fe] | 340 | mtspr ibat0u, r29
|
|---|
| [1f330de] | 341 | mtspr ibat0l, r30
|
|---|
| 342 |
|
|---|
| [bab785fe] | 343 | mtspr dbat0u, r29
|
|---|
| [1f330de] | 344 | mtspr dbat0l, r30
|
|---|
| [bab785fe] | 345 |
|
|---|
| 346 | no_bat:
|
|---|
| [1f330de] | 347 |
|
|---|
| [f3776a3] | 348 | #endif
|
|---|
| [bbeb5e4] | 349 |
|
|---|
| [7b187ef] | 350 | # flush TLB
|
|---|
| 351 |
|
|---|
| 352 | TLB_FLUSH r31
|
|---|
| 353 |
|
|---|
| [01cb210] | 354 | # start the kernel
|
|---|
| [1fbe8da2] | 355 | #
|
|---|
| [e731b0d] | 356 | # pc = PA2KA(BOOT_OFFSET)
|
|---|
| [4872160] | 357 | # r3 = bootinfo (physical address)
|
|---|
| [e731b0d] | 358 | # sprg0 = BOOT_OFFSET
|
|---|
| [2988616b] | 359 | # sprg3 = physical memory size
|
|---|
| [4872160] | 360 | # sp = 0 (enforces the usage of sprg0 as exception stack)
|
|---|
| [01cb210] | 361 |
|
|---|
| [e731b0d] | 362 | lis r31, PA2KA(BOOT_OFFSET)@ha
|
|---|
| 363 | addi r31, r31, PA2KA(BOOT_OFFSET)@l
|
|---|
| [01cb210] | 364 | mtspr srr0, r31
|
|---|
| [1fbe8da2] | 365 |
|
|---|
| [e731b0d] | 366 | lis r31, BOOT_OFFSET@ha
|
|---|
| 367 | addi r31, r31, BOOT_OFFSET@l
|
|---|
| [2988616b] | 368 | mtsprg0 r31
|
|---|
| 369 |
|
|---|
| [4872160] | 370 | # bootinfo starts with a 64 bit integer containing
|
|---|
| 371 | # the physical memory size, get the lower 4 bytes
|
|---|
| 372 |
|
|---|
| 373 | lwz r31, 4(r3)
|
|---|
| [2988616b] | 374 | mtsprg3 r31
|
|---|
| 375 |
|
|---|
| 376 | li sp, 0
|
|---|
| 377 |
|
|---|
| [01cb210] | 378 | mfmsr r31
|
|---|
| 379 | ori r31, r31, (msr_ir | msr_dr)@l
|
|---|
| 380 | mtspr srr1, r31
|
|---|
| [1fbe8da2] | 381 |
|
|---|
| [38fe9d0] | 382 | sync
|
|---|
| 383 | isync
|
|---|
| [1fbe8da2] | 384 | rfi
|
|---|
