| 1 | #
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| 2 | # Copyright (c) 2006 Martin Decky
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| 3 | # All rights reserved.
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| 4 | #
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| 5 | # Redistribution and use in source and binary forms, with or without
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| 6 | # modification, are permitted provided that the following conditions
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| 7 | # are met:
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| 8 | #
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| 9 | # - Redistributions of source code must retain the above copyright
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| 10 | # notice, this list of conditions and the following disclaimer.
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| 11 | # - Redistributions in binary form must reproduce the above copyright
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| 12 | # notice, this list of conditions and the following disclaimer in the
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| 13 | # documentation and/or other materials provided with the distribution.
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| 14 | # - The name of the author may not be used to endorse or promote products
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| 15 | # derived from this software without specific prior written permission.
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| 16 | #
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| 17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | #
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| 28 |
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| 29 | #include <arch/arch.h>
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| 30 | #include <arch/regname.h>
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| 31 |
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| 32 | .set noat
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| 33 | .set noreorder
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| 34 | .set nomacro
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| 35 |
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| 36 | .global start
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| 37 | .global halt
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| 38 | .global jump_to_kernel
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| 39 |
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| 40 | .section BOOTSTRAP
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| 41 |
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| 42 | start:
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| 43 | /*
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| 44 | * Setup the CP0 configuration
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| 45 | * - Disable 64-bit kernel addressing mode
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| 46 | * - DIsable 64-bit supervisor adressing mode
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| 47 | * - Disable 64-bit user addressing mode
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| 48 | */
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| 49 | mfc0 $a0, $status
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| 50 | la $a1, 0xffffff1f
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| 51 | and $a0, $a1, $a0
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| 52 | mtc0 $a0, $status
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| 53 |
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| 54 | /*
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| 55 | * Setup CPU map (on msim this code
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| 56 | * is executed in parallel on all CPUs,
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| 57 | * but it not an issue).
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| 58 | */
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| 59 | la $a0, PA2KA(CPUMAP_OFFSET)
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| 60 |
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| 61 | sw $zero, 0($a0)
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| 62 | sw $zero, 4($a0)
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| 63 | sw $zero, 8($a0)
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| 64 | sw $zero, 12($a0)
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| 65 |
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| 66 | sw $zero, 16($a0)
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| 67 | sw $zero, 20($a0)
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| 68 | sw $zero, 24($a0)
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| 69 | sw $zero, 28($a0)
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| 70 |
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| 71 | sw $zero, 32($a0)
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| 72 | sw $zero, 36($a0)
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| 73 | sw $zero, 40($a0)
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| 74 | sw $zero, 44($a0)
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| 75 |
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| 76 | sw $zero, 48($a0)
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| 77 | sw $zero, 52($a0)
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| 78 | sw $zero, 56($a0)
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| 79 | sw $zero, 60($a0)
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| 80 |
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| 81 | sw $zero, 64($a0)
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| 82 | sw $zero, 68($a0)
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| 83 | sw $zero, 72($a0)
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| 84 | sw $zero, 76($a0)
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| 85 |
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| 86 | sw $zero, 80($a0)
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| 87 | sw $zero, 84($a0)
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| 88 | sw $zero, 88($a0)
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| 89 | sw $zero, 92($a0)
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| 90 |
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| 91 | sw $zero, 96($a0)
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| 92 | sw $zero, 100($a0)
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| 93 | sw $zero, 104($a0)
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| 94 | sw $zero, 108($a0)
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| 95 |
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| 96 | sw $zero, 112($a0)
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| 97 | sw $zero, 116($a0)
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| 98 | sw $zero, 120($a0)
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| 99 | sw $zero, 124($a0)
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| 100 |
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| 101 | lui $a1, 1
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| 102 |
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| 103 | #ifdef MACHINE_msim
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| 104 |
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| 105 | /* Read dorder value */
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| 106 | la $k0, MSIM_DORDER_ADDRESS
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| 107 | lw $k1, ($k0)
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| 108 |
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| 109 | /*
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| 110 | * If we are not running on BSP
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| 111 | * then end in an infinite loop.
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| 112 | */
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| 113 | beq $k1, $zero, bsp
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| 114 | nop
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| 115 |
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| 116 | /* Record CPU presence */
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| 117 | sll $a2, $k1, 2
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| 118 | addu $a2, $a2, $a0
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| 119 | sw $a1, ($a2)
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| 120 |
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| 121 | loop:
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| 122 | j loop
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| 123 | nop
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| 124 |
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| 125 | #endif
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| 126 |
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| 127 | bsp:
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| 128 | /* Record CPU presence */
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| 129 | sw $a1, ($a0)
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| 130 |
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| 131 | /* Setup initial stack */
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| 132 | la $sp, PA2KA(STACK_OFFSET)
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| 133 |
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| 134 | j bootstrap
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| 135 | nop
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| 136 |
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| 137 | .text
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| 138 |
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| 139 | halt:
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| 140 | j halt
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| 141 | nop
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| 142 |
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| 143 | jump_to_kernel:
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| 144 | /*
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| 145 | * TODO:
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| 146 | *
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| 147 | * Make sure that the I-cache, D-cache and memory are mutually
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| 148 | * coherent before passing control to the copied code.
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| 149 | */
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| 150 | j $a0
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| 151 | nop
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