[f761f1eb] | 1 | /*
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[178ec7b] | 2 | * Copyright (C) 2003-2004 Jakub Jermar
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[f761f1eb] | 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | #include <arch/mm/tlb.h>
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[4512d7e] | 30 | #include <mm/asid.h>
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[6ed5352] | 31 | #include <genarch/mm/asid_fifo.h>
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[f761f1eb] | 32 | #include <mm/tlb.h>
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[1084a784] | 33 | #include <mm/page.h>
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[20d50a1] | 34 | #include <mm/as.h>
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[f761f1eb] | 35 | #include <arch/cp0.h>
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| 36 | #include <panic.h>
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| 37 | #include <arch.h>
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[ab08b42] | 38 | #include <symtab.h>
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[1084a784] | 39 | #include <synch/spinlock.h>
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| 40 | #include <print.h>
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[cc205f1] | 41 | #include <debug.h>
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[9c0a9b3] | 42 |
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[1084a784] | 43 | static void tlb_refill_fail(struct exception_regdump *pstate);
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| 44 | static void tlb_invalid_fail(struct exception_regdump *pstate);
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| 45 | static void tlb_modified_fail(struct exception_regdump *pstate);
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| 46 |
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[38a1a84] | 47 | static pte_t *find_mapping_and_check(__address badvaddr);
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[8c5e6c7] | 48 |
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[cc205f1] | 49 | static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, int c, __address pfn);
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[8c5e6c7] | 50 | static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr);
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[38a1a84] | 51 |
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[1084a784] | 52 | /** Initialize TLB
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| 53 | *
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| 54 | * Initialize TLB.
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| 55 | * Invalidate all entries and mark wired entries.
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| 56 | */
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[b00fdde] | 57 | void tlb_arch_init(void)
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[ce031f0] | 58 | {
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[dd14cced] | 59 | int i;
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| 60 |
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[6ed5352] | 61 | asid_fifo_init();
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| 62 |
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[ce031f0] | 63 | cp0_pagemask_write(TLB_PAGE_MASK_16K);
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[dd14cced] | 64 | cp0_entry_hi_write(0);
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| 65 | cp0_entry_lo0_write(0);
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| 66 | cp0_entry_lo1_write(0);
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[ce031f0] | 67 |
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[dd14cced] | 68 | /* Clear and initialize TLB. */
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| 69 |
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| 70 | for (i = 0; i < TLB_ENTRY_COUNT; i++) {
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| 71 | cp0_index_write(i);
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| 72 | tlbwi();
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| 73 | }
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[0bd4f56d] | 74 |
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[a98d2ec] | 75 |
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[ce031f0] | 76 | /*
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| 77 | * The kernel is going to make use of some wired
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[1084a784] | 78 | * entries (e.g. mapping kernel stacks in kseg3).
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[ce031f0] | 79 | */
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| 80 | cp0_wired_write(TLB_WIRED);
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| 81 | }
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| 82 |
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[1084a784] | 83 | /** Process TLB Refill Exception
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| 84 | *
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| 85 | * Process TLB Refill Exception.
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| 86 | *
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| 87 | * @param pstate Interrupted register context.
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| 88 | */
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[909c6e3] | 89 | void tlb_refill(struct exception_regdump *pstate)
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[1084a784] | 90 | {
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[cc205f1] | 91 | entry_lo_t lo;
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[8c5e6c7] | 92 | entry_hi_t hi;
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[1084a784] | 93 | __address badvaddr;
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| 94 | pte_t *pte;
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[fd3c9e5] | 95 |
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[1084a784] | 96 | badvaddr = cp0_badvaddr_read();
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[fd3c9e5] | 97 |
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[20d50a1] | 98 | spinlock_lock(&AS->lock);
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[8c5e6c7] | 99 |
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[38a1a84] | 100 | pte = find_mapping_and_check(badvaddr);
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[1084a784] | 101 | if (!pte)
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| 102 | goto fail;
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[38a1a84] | 103 |
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[1084a784] | 104 | /*
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[38a1a84] | 105 | * Record access to PTE.
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[1084a784] | 106 | */
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[38a1a84] | 107 | pte->a = 1;
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| 108 |
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[20d50a1] | 109 | prepare_entry_hi(&hi, AS->asid, badvaddr);
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[a016b63] | 110 | prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->lo.d, pte->lo.c, pte->lo.pfn);
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[1084a784] | 111 |
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| 112 | /*
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| 113 | * New entry is to be inserted into TLB
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| 114 | */
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[8c5e6c7] | 115 | cp0_entry_hi_write(hi.value);
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[1084a784] | 116 | if ((badvaddr/PAGE_SIZE) % 2 == 0) {
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[cc205f1] | 117 | cp0_entry_lo0_write(lo.value);
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[1084a784] | 118 | cp0_entry_lo1_write(0);
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| 119 | }
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| 120 | else {
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| 121 | cp0_entry_lo0_write(0);
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[cc205f1] | 122 | cp0_entry_lo1_write(lo.value);
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[1084a784] | 123 | }
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[0bd4f56d] | 124 | cp0_pagemask_write(TLB_PAGE_MASK_16K);
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[1084a784] | 125 | tlbwr();
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| 126 |
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[20d50a1] | 127 | spinlock_unlock(&AS->lock);
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[1084a784] | 128 | return;
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| 129 |
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| 130 | fail:
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[20d50a1] | 131 | spinlock_unlock(&AS->lock);
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[1084a784] | 132 | tlb_refill_fail(pstate);
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| 133 | }
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| 134 |
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[38a1a84] | 135 | /** Process TLB Invalid Exception
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| 136 | *
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| 137 | * Process TLB Invalid Exception.
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| 138 | *
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| 139 | * @param pstate Interrupted register context.
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| 140 | */
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[1084a784] | 141 | void tlb_invalid(struct exception_regdump *pstate)
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| 142 | {
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[cc205f1] | 143 | tlb_index_t index;
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[38a1a84] | 144 | __address badvaddr;
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[cc205f1] | 145 | entry_lo_t lo;
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[8c5e6c7] | 146 | entry_hi_t hi;
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[38a1a84] | 147 | pte_t *pte;
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| 148 |
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| 149 | badvaddr = cp0_badvaddr_read();
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| 150 |
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| 151 | /*
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| 152 | * Locate the faulting entry in TLB.
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| 153 | */
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[8c5e6c7] | 154 | hi.value = cp0_entry_hi_read();
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| 155 | prepare_entry_hi(&hi, hi.asid, badvaddr);
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| 156 | cp0_entry_hi_write(hi.value);
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[38a1a84] | 157 | tlbp();
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[cc205f1] | 158 | index.value = cp0_index_read();
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[38a1a84] | 159 |
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[20d50a1] | 160 | spinlock_lock(&AS->lock);
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[38a1a84] | 161 |
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| 162 | /*
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| 163 | * Fail if the entry is not in TLB.
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| 164 | */
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[cc205f1] | 165 | if (index.p) {
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| 166 | printf("TLB entry not found.\n");
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[38a1a84] | 167 | goto fail;
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[cc205f1] | 168 | }
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[38a1a84] | 169 |
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| 170 | pte = find_mapping_and_check(badvaddr);
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| 171 | if (!pte)
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| 172 | goto fail;
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| 173 |
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| 174 | /*
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| 175 | * Read the faulting TLB entry.
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| 176 | */
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| 177 | tlbr();
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| 178 |
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| 179 | /*
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| 180 | * Record access to PTE.
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| 181 | */
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| 182 | pte->a = 1;
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| 183 |
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[a016b63] | 184 | prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->lo.d, pte->lo.c, pte->lo.pfn);
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[38a1a84] | 185 |
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| 186 | /*
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| 187 | * The entry is to be updated in TLB.
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| 188 | */
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| 189 | if ((badvaddr/PAGE_SIZE) % 2 == 0)
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[cc205f1] | 190 | cp0_entry_lo0_write(lo.value);
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[38a1a84] | 191 | else
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[cc205f1] | 192 | cp0_entry_lo1_write(lo.value);
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[0bd4f56d] | 193 | cp0_pagemask_write(TLB_PAGE_MASK_16K);
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[38a1a84] | 194 | tlbwi();
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| 195 |
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[20d50a1] | 196 | spinlock_unlock(&AS->lock);
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[38a1a84] | 197 | return;
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| 198 |
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| 199 | fail:
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[20d50a1] | 200 | spinlock_unlock(&AS->lock);
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[1084a784] | 201 | tlb_invalid_fail(pstate);
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| 202 | }
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| 203 |
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[38a1a84] | 204 | /** Process TLB Modified Exception
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| 205 | *
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| 206 | * Process TLB Modified Exception.
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| 207 | *
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| 208 | * @param pstate Interrupted register context.
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| 209 | */
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[1084a784] | 210 | void tlb_modified(struct exception_regdump *pstate)
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| 211 | {
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[cc205f1] | 212 | tlb_index_t index;
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[38a1a84] | 213 | __address badvaddr;
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[cc205f1] | 214 | entry_lo_t lo;
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[8c5e6c7] | 215 | entry_hi_t hi;
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[38a1a84] | 216 | pte_t *pte;
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| 217 |
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| 218 | badvaddr = cp0_badvaddr_read();
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| 219 |
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| 220 | /*
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| 221 | * Locate the faulting entry in TLB.
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| 222 | */
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[8c5e6c7] | 223 | hi.value = cp0_entry_hi_read();
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| 224 | prepare_entry_hi(&hi, hi.asid, badvaddr);
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| 225 | cp0_entry_hi_write(hi.value);
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[38a1a84] | 226 | tlbp();
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[cc205f1] | 227 | index.value = cp0_index_read();
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[38a1a84] | 228 |
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[20d50a1] | 229 | spinlock_lock(&AS->lock);
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[38a1a84] | 230 |
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| 231 | /*
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| 232 | * Fail if the entry is not in TLB.
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| 233 | */
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[cc205f1] | 234 | if (index.p) {
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| 235 | printf("TLB entry not found.\n");
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[38a1a84] | 236 | goto fail;
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[cc205f1] | 237 | }
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[38a1a84] | 238 |
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| 239 | pte = find_mapping_and_check(badvaddr);
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| 240 | if (!pte)
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| 241 | goto fail;
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| 242 |
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| 243 | /*
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| 244 | * Fail if the page is not writable.
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| 245 | */
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| 246 | if (!pte->w)
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| 247 | goto fail;
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| 248 |
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| 249 | /*
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| 250 | * Read the faulting TLB entry.
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| 251 | */
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| 252 | tlbr();
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| 253 |
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| 254 | /*
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| 255 | * Record access and write to PTE.
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| 256 | */
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| 257 | pte->a = 1;
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[a016b63] | 258 | pte->lo.d = 1;
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[38a1a84] | 259 |
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[a016b63] | 260 | prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->w, pte->lo.c, pte->lo.pfn);
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[38a1a84] | 261 |
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| 262 | /*
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| 263 | * The entry is to be updated in TLB.
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| 264 | */
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| 265 | if ((badvaddr/PAGE_SIZE) % 2 == 0)
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[cc205f1] | 266 | cp0_entry_lo0_write(lo.value);
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[38a1a84] | 267 | else
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[cc205f1] | 268 | cp0_entry_lo1_write(lo.value);
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[0bd4f56d] | 269 | cp0_pagemask_write(TLB_PAGE_MASK_16K);
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[38a1a84] | 270 | tlbwi();
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| 271 |
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[20d50a1] | 272 | spinlock_unlock(&AS->lock);
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[38a1a84] | 273 | return;
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| 274 |
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| 275 | fail:
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[20d50a1] | 276 | spinlock_unlock(&AS->lock);
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[1084a784] | 277 | tlb_modified_fail(pstate);
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| 278 | }
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| 279 |
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| 280 | void tlb_refill_fail(struct exception_regdump *pstate)
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[f761f1eb] | 281 | {
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[38de8a5] | 282 | char *symbol = "";
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| 283 | char *sym2 = "";
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| 284 |
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[3156582] | 285 | char *s = get_symtab_entry(pstate->epc);
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| 286 | if (s)
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| 287 | symbol = s;
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| 288 | s = get_symtab_entry(pstate->ra);
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| 289 | if (s)
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| 290 | sym2 = s;
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[1084a784] | 291 | panic("%X: TLB Refill Exception at %X(%s<-%s)\n", cp0_badvaddr_read(), pstate->epc, symbol, sym2);
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[f761f1eb] | 292 | }
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| 293 |
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[1084a784] | 294 |
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| 295 | void tlb_invalid_fail(struct exception_regdump *pstate)
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[f761f1eb] | 296 | {
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[ab08b42] | 297 | char *symbol = "";
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| 298 |
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[3156582] | 299 | char *s = get_symtab_entry(pstate->epc);
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| 300 | if (s)
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| 301 | symbol = s;
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[38a1a84] | 302 | panic("%X: TLB Invalid Exception at %X(%s)\n", cp0_badvaddr_read(), pstate->epc, symbol);
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[f761f1eb] | 303 | }
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| 304 |
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[1084a784] | 305 | void tlb_modified_fail(struct exception_regdump *pstate)
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[ce031f0] | 306 | {
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| 307 | char *symbol = "";
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| 308 |
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| 309 | char *s = get_symtab_entry(pstate->epc);
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| 310 | if (s)
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| 311 | symbol = s;
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[38a1a84] | 312 | panic("%X: TLB Modified Exception at %X(%s)\n", cp0_badvaddr_read(), pstate->epc, symbol);
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[ce031f0] | 313 | }
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| 314 |
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[38a1a84] | 315 | /** Try to find PTE for faulting address
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| 316 | *
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| 317 | * Try to find PTE for faulting address.
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[20d50a1] | 318 | * The AS->lock must be held on entry to this function.
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[38a1a84] | 319 | *
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| 320 | * @param badvaddr Faulting virtual address.
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| 321 | *
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| 322 | * @return PTE on success, NULL otherwise.
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| 323 | */
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| 324 | pte_t *find_mapping_and_check(__address badvaddr)
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| 325 | {
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[cc205f1] | 326 | entry_hi_t hi;
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[38a1a84] | 327 | pte_t *pte;
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| 328 |
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[cc205f1] | 329 | hi.value = cp0_entry_hi_read();
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[38a1a84] | 330 |
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| 331 | /*
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| 332 | * Handler cannot succeed if the ASIDs don't match.
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| 333 | */
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[20d50a1] | 334 | if (hi.asid != AS->asid) {
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| 335 | printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid);
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[38a1a84] | 336 | return NULL;
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[cc205f1] | 337 | }
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[20d50a1] | 338 |
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| 339 | /*
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| 340 | * Check if the mapping exists in page tables.
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| 341 | */
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[ef67bab] | 342 | pte = page_mapping_find(AS, badvaddr);
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[20d50a1] | 343 | if (pte && pte->lo.v) {
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| 344 | /*
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| 345 | * Mapping found in page tables.
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| 346 | * Immediately succeed.
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| 347 | */
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| 348 | return pte;
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| 349 | } else {
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| 350 | /*
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| 351 | * Mapping not found in page tables.
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| 352 | * Resort to higher-level page fault handler.
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| 353 | */
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| 354 | if (as_page_fault(badvaddr)) {
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| 355 | /*
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| 356 | * The higher-level page fault handler succeeded,
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| 357 | * The mapping ought to be in place.
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| 358 | */
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[ef67bab] | 359 | pte = page_mapping_find(AS, badvaddr);
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[20d50a1] | 360 | ASSERT(pte && pte->lo.v);
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| 361 | return pte;
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| 362 | }
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| 363 | }
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| 364 |
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[38a1a84] | 365 | /*
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| 366 | * Handler cannot succeed if badvaddr has no mapping.
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| 367 | */
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[cc205f1] | 368 | if (!pte) {
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[086d4fd] | 369 | printf("No such mapping.\n");
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[38a1a84] | 370 | return NULL;
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[cc205f1] | 371 | }
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[38a1a84] | 372 |
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| 373 | /*
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| 374 | * Handler cannot succeed if the mapping is marked as invalid.
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| 375 | */
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[a016b63] | 376 | if (!pte->lo.v) {
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[cc205f1] | 377 | printf("Invalid mapping.\n");
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[38a1a84] | 378 | return NULL;
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[cc205f1] | 379 | }
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[38a1a84] | 380 |
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| 381 | return pte;
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| 382 | }
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| 383 |
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[cc205f1] | 384 | void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, int c, __address pfn)
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[38a1a84] | 385 | {
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[8c5e6c7] | 386 | lo->value = 0;
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[38a1a84] | 387 | lo->g = g;
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| 388 | lo->v = v;
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| 389 | lo->d = d;
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| 390 | lo->c = c;
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| 391 | lo->pfn = pfn;
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[8c5e6c7] | 392 | }
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| 393 |
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| 394 | void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr)
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| 395 | {
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| 396 | hi->value = (((addr/PAGE_SIZE)/2)*PAGE_SIZE*2);
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| 397 | hi->asid = asid;
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[38a1a84] | 398 | }
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[b00fdde] | 399 |
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[02055415] | 400 | /** Print contents of TLB. */
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[b00fdde] | 401 | void tlb_print(void)
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| 402 | {
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[0bd4f56d] | 403 | page_mask_t mask;
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[02055415] | 404 | entry_lo_t lo0, lo1;
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[f9425006] | 405 | entry_hi_t hi, hi_save;
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[02055415] | 406 | int i;
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| 407 |
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[f9425006] | 408 | hi_save.value = cp0_entry_hi_read();
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| 409 |
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[02055415] | 410 | printf("TLB:\n");
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| 411 | for (i = 0; i < TLB_ENTRY_COUNT; i++) {
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| 412 | cp0_index_write(i);
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| 413 | tlbr();
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| 414 |
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[0bd4f56d] | 415 | mask.value = cp0_pagemask_read();
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[02055415] | 416 | hi.value = cp0_entry_hi_read();
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| 417 | lo0.value = cp0_entry_lo0_read();
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| 418 | lo1.value = cp0_entry_lo1_read();
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| 419 |
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[0bd4f56d] | 420 | printf("%d: asid=%d, vpn2=%d, mask=%d\tg[0]=%d, v[0]=%d, d[0]=%d, c[0]=%B, pfn[0]=%d\n"
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| 421 | "\t\t\t\tg[1]=%d, v[1]=%d, d[1]=%d, c[1]=%B, pfn[1]=%d\n",
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| 422 | i, hi.asid, hi.vpn2, mask.mask, lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn,
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[02055415] | 423 | lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);
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| 424 | }
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[f9425006] | 425 |
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| 426 | cp0_entry_hi_write(hi_save.value);
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[b00fdde] | 427 | }
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[a98d2ec] | 428 |
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[8ad925c] | 429 | /** Invalidate all not wired TLB entries. */
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[a98d2ec] | 430 | void tlb_invalidate_all(void)
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| 431 | {
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[dd14cced] | 432 | ipl_t ipl;
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| 433 | entry_lo_t lo0, lo1;
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[f9425006] | 434 | entry_hi_t hi_save;
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[a98d2ec] | 435 | int i;
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| 436 |
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[f9425006] | 437 | hi_save.value = cp0_entry_hi_read();
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[dd14cced] | 438 | ipl = interrupts_disable();
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[a98d2ec] | 439 |
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[8ad925c] | 440 | for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) {
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[a98d2ec] | 441 | cp0_index_write(i);
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[dd14cced] | 442 | tlbr();
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| 443 |
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| 444 | lo0.value = cp0_entry_lo0_read();
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| 445 | lo1.value = cp0_entry_lo1_read();
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| 446 |
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| 447 | lo0.v = 0;
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| 448 | lo1.v = 0;
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| 449 |
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| 450 | cp0_entry_lo0_write(lo0.value);
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| 451 | cp0_entry_lo1_write(lo1.value);
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| 452 |
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[a98d2ec] | 453 | tlbwi();
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| 454 | }
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[dd14cced] | 455 |
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| 456 | interrupts_restore(ipl);
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[f9425006] | 457 | cp0_entry_hi_write(hi_save.value);
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[a98d2ec] | 458 | }
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| 459 |
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| 460 | /** Invalidate all TLB entries belonging to specified address space.
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| 461 | *
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| 462 | * @param asid Address space identifier.
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| 463 | */
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| 464 | void tlb_invalidate_asid(asid_t asid)
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| 465 | {
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[dd14cced] | 466 | ipl_t ipl;
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| 467 | entry_lo_t lo0, lo1;
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[f9425006] | 468 | entry_hi_t hi, hi_save;
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[a98d2ec] | 469 | int i;
|
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| 470 |
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[dd14cced] | 471 | ASSERT(asid != ASID_INVALID);
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| 472 |
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[f9425006] | 473 | hi_save.value = cp0_entry_hi_read();
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[dd14cced] | 474 | ipl = interrupts_disable();
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| 475 |
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[a98d2ec] | 476 | for (i = 0; i < TLB_ENTRY_COUNT; i++) {
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| 477 | cp0_index_write(i);
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| 478 | tlbr();
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| 479 |
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[dd14cced] | 480 | hi.value = cp0_entry_hi_read();
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| 481 |
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[a98d2ec] | 482 | if (hi.asid == asid) {
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[dd14cced] | 483 | lo0.value = cp0_entry_lo0_read();
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| 484 | lo1.value = cp0_entry_lo1_read();
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| 485 |
|
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| 486 | lo0.v = 0;
|
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| 487 | lo1.v = 0;
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| 488 |
|
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| 489 | cp0_entry_lo0_write(lo0.value);
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| 490 | cp0_entry_lo1_write(lo1.value);
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| 491 |
|
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[a98d2ec] | 492 | tlbwi();
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| 493 | }
|
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| 494 | }
|
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[dd14cced] | 495 |
|
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| 496 | interrupts_restore(ipl);
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[f9425006] | 497 | cp0_entry_hi_write(hi_save.value);
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[a98d2ec] | 498 | }
|
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| 499 |
|
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[4512d7e] | 500 | /** Invalidate TLB entries for specified page range belonging to specified address space.
|
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[a98d2ec] | 501 | *
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| 502 | * @param asid Address space identifier.
|
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[4512d7e] | 503 | * @param page First page whose TLB entry is to be invalidated.
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| 504 | * @param cnt Number of entries to invalidate.
|
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[a98d2ec] | 505 | */
|
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[4512d7e] | 506 | void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)
|
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[a98d2ec] | 507 | {
|
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[4512d7e] | 508 | int i;
|
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[dd14cced] | 509 | ipl_t ipl;
|
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| 510 | entry_lo_t lo0, lo1;
|
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[f9425006] | 511 | entry_hi_t hi, hi_save;
|
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[a98d2ec] | 512 | tlb_index_t index;
|
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[dd14cced] | 513 |
|
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| 514 | ASSERT(asid != ASID_INVALID);
|
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| 515 |
|
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[f9425006] | 516 | hi_save.value = cp0_entry_hi_read();
|
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[dd14cced] | 517 | ipl = interrupts_disable();
|
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[a98d2ec] | 518 |
|
---|
[4512d7e] | 519 | for (i = 0; i < cnt; i++) {
|
---|
| 520 | hi.value = 0;
|
---|
| 521 | prepare_entry_hi(&hi, asid, page + i * PAGE_SIZE);
|
---|
| 522 | cp0_entry_hi_write(hi.value);
|
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[dd14cced] | 523 |
|
---|
[4512d7e] | 524 | tlbp();
|
---|
| 525 | index.value = cp0_index_read();
|
---|
[a98d2ec] | 526 |
|
---|
[4512d7e] | 527 | if (!index.p) {
|
---|
| 528 | /* Entry was found, index register contains valid index. */
|
---|
| 529 | tlbr();
|
---|
[dd14cced] | 530 |
|
---|
[4512d7e] | 531 | lo0.value = cp0_entry_lo0_read();
|
---|
| 532 | lo1.value = cp0_entry_lo1_read();
|
---|
[dd14cced] | 533 |
|
---|
[4512d7e] | 534 | lo0.v = 0;
|
---|
| 535 | lo1.v = 0;
|
---|
[dd14cced] | 536 |
|
---|
[4512d7e] | 537 | cp0_entry_lo0_write(lo0.value);
|
---|
| 538 | cp0_entry_lo1_write(lo1.value);
|
---|
[dd14cced] | 539 |
|
---|
[4512d7e] | 540 | tlbwi();
|
---|
| 541 | }
|
---|
[a98d2ec] | 542 | }
|
---|
[dd14cced] | 543 |
|
---|
| 544 | interrupts_restore(ipl);
|
---|
[f9425006] | 545 | cp0_entry_hi_write(hi_save.value);
|
---|
[a98d2ec] | 546 | }
|
---|