[f761f1eb] | 1 | /*
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[178ec7b] | 2 | * Copyright (C) 2003-2004 Jakub Jermar
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[f761f1eb] | 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | #include <arch/interrupt.h>
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| 30 | #include <arch/types.h>
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| 31 | #include <arch.h>
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| 32 | #include <arch/cp0.h>
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| 33 | #include <time/clock.h>
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| 34 | #include <panic.h>
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[3156582] | 35 | #include <print.h>
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| 36 | #include <symtab.h>
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| 37 | #include <arch/drivers/arc.h>
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| 38 |
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| 39 | static void print_regdump(struct exception_regdump *pstate)
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| 40 | {
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| 41 | char *pcsymbol = "";
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| 42 | char *rasymbol = "";
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| 43 |
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| 44 | char *s = get_symtab_entry(pstate->epc);
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| 45 | if (s)
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| 46 | pcsymbol = s;
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| 47 | s = get_symtab_entry(pstate->ra);
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| 48 | if (s)
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| 49 | rasymbol = s;
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| 50 |
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| 51 | printf("PC: %X(%s) RA: %X(%s)\n",pstate->epc,pcsymbol,
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| 52 | pstate->ra,rasymbol);
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| 53 | }
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[f761f1eb] | 54 |
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[22f7769] | 55 | /** Disable interrupts.
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| 56 | *
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| 57 | * @return Old interrupt priority level.
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| 58 | */
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| 59 | ipl_t interrupts_disable(void)
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[f761f1eb] | 60 | {
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[22f7769] | 61 | ipl_t ipl = (ipl_t) cp0_status_read();
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| 62 | cp0_status_write(ipl & ~cp0_status_ie_enabled_bit);
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| 63 | return ipl;
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[f761f1eb] | 64 | }
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| 65 |
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[22f7769] | 66 | /** Enable interrupts.
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| 67 | *
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| 68 | * @return Old interrupt priority level.
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| 69 | */
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| 70 | ipl_t interrupts_enable(void)
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[f761f1eb] | 71 | {
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[22f7769] | 72 | ipl_t ipl = (ipl_t) cp0_status_read();
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| 73 | cp0_status_write(ipl | cp0_status_ie_enabled_bit);
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| 74 | return ipl;
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[f761f1eb] | 75 | }
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| 76 |
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[22f7769] | 77 | /** Restore interrupt priority level.
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| 78 | *
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| 79 | * @param ipl Saved interrupt priority level.
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| 80 | */
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| 81 | void interrupts_restore(ipl_t ipl)
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[f761f1eb] | 82 | {
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[22f7769] | 83 | cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit));
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[f761f1eb] | 84 | }
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| 85 |
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[22f7769] | 86 | /** Read interrupt priority level.
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| 87 | *
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| 88 | * @return Current interrupt priority level.
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| 89 | */
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| 90 | ipl_t interrupts_read(void)
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[f761f1eb] | 91 | {
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[76cec1e] | 92 | return cp0_status_read();
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[f761f1eb] | 93 | }
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| 94 |
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[3156582] | 95 | void interrupt(struct exception_regdump *pstate)
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[f761f1eb] | 96 | {
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| 97 | __u32 cause;
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[e41c47e] | 98 | int i;
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| 99 |
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[f761f1eb] | 100 | /* decode interrupt number and process the interrupt */
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[e41c47e] | 101 | cause = (cp0_cause_read() >> 8) &0xff;
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| 102 |
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| 103 | for (i = 0; i < 8; i++) {
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| 104 | if (cause & (1 << i)) {
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| 105 | switch (i) {
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| 106 | case 0: /* SW0 - Software interrupt 0 */
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[3156582] | 107 | cp0_cause_write(cp0_cause_read() & ~(1 << 8)); /* clear SW0 interrupt */
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[e41c47e] | 108 | break;
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| 109 | case 1: /* SW1 - Software interrupt 1 */
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[3156582] | 110 | cp0_cause_write(cp0_cause_read() & ~(1 << 9)); /* clear SW1 interrupt */
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[e41c47e] | 111 | break;
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| 112 | case 2: /* IRQ0 */
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| 113 | case 3: /* IRQ1 */
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| 114 | case 4: /* IRQ2 */
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| 115 | case 5: /* IRQ3 */
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| 116 | case 6: /* IRQ4 */
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[3156582] | 117 | print_regdump(pstate);
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[e41c47e] | 118 | panic("unhandled interrupt %d\n", i);
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| 119 | break;
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[24241cf] | 120 | case TIMER_INTERRUPT:
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| 121 | /* clear timer interrupt & set new */
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| 122 | cp0_compare_write(cp0_count_read() + cp0_compare_value);
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[e41c47e] | 123 | clock();
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| 124 | break;
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| 125 | }
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| 126 | }
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| 127 | }
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[f761f1eb] | 128 |
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| 129 | }
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