source: mainline/arch/mips32/include/mm/tlb.h@ fd3c9e5

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since fd3c9e5 was cc205f1, checked in by Jakub Jermar <jakub@…>, 20 years ago

Add mm/mapping1 test.
(Will not make it past TLB Invalid exception on mips32.)
Fixes in asid.c.
Make TLB register types union with u32 value.
Implement tlb_invalidate() for mips32.
(TLB invalidation and shootdown path will have to be revised.)

  • Property mode set to 100644
File size: 3.5 KB
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1/*
2 * Copyright (C) 2003-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __mips32_TLB_H__
30#define __mips32_TLB_H__
31
32#include <arch/exception.h>
33
34#define TLB_SIZE 48
35
36#define TLB_WIRED 1
37#define TLB_KSTACK_WIRED_INDEX 0
38
39#define TLB_PAGE_MASK_16K (0x3<<13)
40
41#define PAGE_UNCACHED 2
42#define PAGE_CACHEABLE_EXC_WRITE 5
43
44union entry_lo {
45 struct {
46 unsigned g : 1; /* global bit */
47 unsigned v : 1; /* valid bit */
48 unsigned d : 1; /* dirty/write-protect bit */
49 unsigned c : 3; /* cache coherency attribute */
50 unsigned pfn : 24; /* frame number */
51 unsigned zero: 2; /* zero */
52 } __attribute__ ((packed));
53 __u32 value;
54};
55
56struct pte {
57 unsigned g : 1; /* global bit */
58 unsigned v : 1; /* valid bit */
59 unsigned d : 1; /* dirty/write-protect bit */
60 unsigned c : 3; /* cache coherency attribute */
61 unsigned pfn : 24; /* frame number */
62 unsigned w : 1; /* writable */
63 unsigned a : 1; /* accessed */
64} __attribute__ ((packed));
65
66union entry_hi {
67 struct {
68 unsigned asid : 8;
69 unsigned : 5;
70 unsigned vpn2 : 19;
71 } __attribute__ ((packed));
72 __u32 value;
73};
74
75union page_mask {
76 struct {
77 unsigned : 13;
78 unsigned mask : 12;
79 unsigned : 7;
80 } __attribute__ ((packed));
81 __u32 value;
82};
83
84union index {
85 struct {
86 unsigned index : 4;
87 unsigned : 27;
88 unsigned p : 1;
89 } __attribute__ ((packed));
90 __u32 value;
91};
92
93typedef union entry_lo entry_lo_t;
94typedef union entry_hi entry_hi_t;
95typedef union page_mask page_mask_t;
96typedef union index tlb_index_t;
97
98/** Probe TLB for Matching Entry
99 *
100 * Probe TLB for Matching Entry.
101 */
102static inline void tlbp(void)
103{
104 __asm__ volatile ("tlbp\n\t");
105}
106
107
108/** Read Indexed TLB Entry
109 *
110 * Read Indexed TLB Entry.
111 */
112static inline void tlbr(void)
113{
114 __asm__ volatile ("tlbr\n\t");
115}
116
117/** Write Indexed TLB Entry
118 *
119 * Write Indexed TLB Entry.
120 */
121static inline void tlbwi(void)
122{
123 __asm__ volatile ("tlbwi\n\t");
124}
125
126/** Write Random TLB Entry
127 *
128 * Write Random TLB Entry.
129 */
130static inline void tlbwr(void)
131{
132 __asm__ volatile ("tlbwr\n\t");
133}
134
135extern void tlb_invalid(struct exception_regdump *pstate);
136extern void tlb_refill(struct exception_regdump *pstate);
137extern void tlb_modified(struct exception_regdump *pstate);
138
139#endif
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