source: mainline/arch/ia32/src/smp/apic.c@ 9149135

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 9149135 was 9149135, checked in by Jakub Jermar <jakub@…>, 20 years ago

SMP cleanup continued.
Add nice type for IO APIC ID register.
Replace some magic numbers with more descriptive macros.
  • Property mode set to 100644
File size: 12.5 KB
Line 
1/*
2 * Copyright (C) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <arch/types.h>
30#include <arch/smp/apic.h>
31#include <arch/smp/ap.h>
32#include <arch/smp/mps.h>
33#include <mm/page.h>
34#include <time/delay.h>
35#include <arch/interrupt.h>
36#include <print.h>
37#include <arch/asm.h>
38#include <arch.h>
39
40#ifdef CONFIG_SMP
41
42/*
43 * Advanced Programmable Interrupt Controller for SMP systems.
44 * Tested on:
45 * Bochs 2.0.2 - Bochs 2.2 with 2-8 CPUs
46 * Simics 2.0.28 - Simics 2.2.19 2-8 CPUs
47 * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
48 * ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
49 * MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
50 */
51
52/*
53 * These variables either stay configured as initilalized, or are changed by
54 * the MP configuration code.
55 *
56 * Pay special attention to the volatile keyword. Without it, gcc -O2 would
57 * optimize the code too much and accesses to l_apic and io_apic, that must
58 * always be 32-bit, would use byte oriented instructions.
59 */
60volatile __u32 *l_apic = (__u32 *) 0xfee00000;
61volatile __u32 *io_apic = (__u32 *) 0xfec00000;
62
63__u32 apic_id_mask = 0;
64
65static int apic_poll_errors(void);
66
67#ifdef LAPIC_VERBOSE
68static char *delmod_str[] = {
69 "Fixed",
70 "Lowest Priority",
71 "SMI",
72 "Reserved",
73 "NMI",
74 "INIT",
75 "STARTUP",
76 "ExtInt"
77};
78
79static char *destmod_str[] = {
80 "Physical",
81 "Logical"
82};
83
84static char *trigmod_str[] = {
85 "Edge",
86 "Level"
87};
88
89static char *mask_str[] = {
90 "Unmasked",
91 "Masked"
92};
93
94static char *delivs_str[] = {
95 "Idle",
96 "Send Pending"
97};
98
99static char *tm_mode_str[] = {
100 "One-shot",
101 "Periodic"
102};
103
104static char *intpol_str[] = {
105 "Polarity High",
106 "Polarity Low"
107};
108#endif /* LAPIC_VERBOSE */
109
110/** Initialize APIC on BSP. */
111void apic_init(void)
112{
113 io_apic_id_t idreg;
114 int i;
115
116 trap_register(VECTOR_APIC_SPUR, apic_spurious);
117
118 enable_irqs_function = io_apic_enable_irqs;
119 disable_irqs_function = io_apic_disable_irqs;
120 eoi_function = l_apic_eoi;
121
122 /*
123 * Configure interrupt routing.
124 * IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
125 * Other interrupts will be forwarded to the lowest priority CPU.
126 */
127 io_apic_disable_irqs(0xffff);
128 trap_register(VECTOR_CLK, l_apic_timer_interrupt);
129 for (i = 0; i < IRQ_COUNT; i++) {
130 int pin;
131
132 if ((pin = smp_irq_to_pin(i)) != -1) {
133 io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI);
134 }
135 }
136
137 /*
138 * Ensure that io_apic has unique ID.
139 */
140 idreg.value = io_apic_read(IOAPICID);
141 if ((1<<idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */
142 for (i = 0; i < APIC_ID_COUNT; i++) {
143 if (!((1<<i) & apic_id_mask)) {
144 idreg.apic_id = i;
145 io_apic_write(IOAPICID, idreg.value);
146 break;
147 }
148 }
149 }
150
151 /*
152 * Configure the BSP's lapic.
153 */
154 l_apic_init();
155
156 l_apic_debug();
157}
158
159/** APIC spurious interrupt handler.
160 *
161 * @param n Interrupt vector.
162 * @param stack Interrupted stack.
163 */
164void apic_spurious(__u8 n, __native stack[])
165{
166 printf("cpu%d: APIC spurious interrupt\n", CPU->id);
167}
168
169/** Poll for APIC errors.
170 *
171 * Examine Error Status Register and report all errors found.
172 *
173 * @return 0 on error, 1 on success.
174 */
175int apic_poll_errors(void)
176{
177 esr_t esr;
178
179 esr.value = l_apic[ESR];
180
181 if (esr.send_checksum_error)
182 printf("Send Checksum Error\n");
183 if (esr.receive_checksum_error)
184 printf("Receive Checksum Error\n");
185 if (esr.send_accept_error)
186 printf("Send Accept Error\n");
187 if (esr.receive_accept_error)
188 printf("Receive Accept Error\n");
189 if (esr.send_illegal_vector)
190 printf("Send Illegal Vector\n");
191 if (esr.received_illegal_vector)
192 printf("Received Illegal Vector\n");
193 if (esr.illegal_register_address)
194 printf("Illegal Register Address\n");
195
196 return !esr.err_bitmap;
197}
198
199/** Send all CPUs excluding CPU IPI vector.
200 *
201 * @param vector Interrupt vector to be sent.
202 *
203 * @return 0 on failure, 1 on success.
204 */
205int l_apic_broadcast_custom_ipi(__u8 vector)
206{
207 icr_t icr;
208
209 icr.lo = l_apic[ICRlo];
210 icr.delmod = DELMOD_FIXED;
211 icr.destmod = DESTMOD_LOGIC;
212 icr.level = LEVEL_ASSERT;
213 icr.shorthand = SHORTHAND_ALL_EXCL;
214 icr.trigger_mode = TRIGMOD_LEVEL;
215 icr.vector = vector;
216
217 l_apic[ICRlo] = icr.lo;
218
219 icr.lo = l_apic[ICRlo];
220 if (icr.delivs == DELIVS_PENDING)
221 printf("IPI is pending.\n");
222
223 return apic_poll_errors();
224}
225
226/** Universal Start-up Algorithm for bringing up the AP processors.
227 *
228 * @param apicid APIC ID of the processor to be brought up.
229 *
230 * @return 0 on failure, 1 on success.
231 */
232int l_apic_send_init_ipi(__u8 apicid)
233{
234 icr_t icr;
235 int i;
236
237 /*
238 * Read the ICR register in and zero all non-reserved fields.
239 */
240 icr.lo = l_apic[ICRlo];
241 icr.hi = l_apic[ICRhi];
242
243 icr.delmod = DELMOD_INIT;
244 icr.destmod = DESTMOD_PHYS;
245 icr.level = LEVEL_ASSERT;
246 icr.trigger_mode = TRIGMOD_LEVEL;
247 icr.shorthand = SHORTHAND_NONE;
248 icr.vector = 0;
249 icr.dest = apicid;
250
251 l_apic[ICRhi] = icr.hi;
252 l_apic[ICRlo] = icr.lo;
253
254 /*
255 * According to MP Specification, 20us should be enough to
256 * deliver the IPI.
257 */
258 delay(20);
259
260 if (!apic_poll_errors()) return 0;
261
262 icr.lo = l_apic[ICRlo];
263 if (icr.delivs == DELIVS_PENDING)
264 printf("IPI is pending.\n");
265
266 icr.delmod = DELMOD_INIT;
267 icr.destmod = DESTMOD_PHYS;
268 icr.level = LEVEL_DEASSERT;
269 icr.shorthand = SHORTHAND_NONE;
270 icr.trigger_mode = TRIGMOD_LEVEL;
271 icr.vector = 0;
272 l_apic[ICRlo] = icr.lo;
273
274 /*
275 * Wait 10ms as MP Specification specifies.
276 */
277 delay(10000);
278
279 if (!is_82489DX_apic(l_apic[LAVR])) {
280 /*
281 * If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
282 */
283 for (i = 0; i<2; i++) {
284 icr.lo = l_apic[ICRlo];
285 icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */
286 icr.delmod = DELMOD_STARTUP;
287 icr.destmod = DESTMOD_PHYS;
288 icr.level = LEVEL_ASSERT;
289 icr.shorthand = SHORTHAND_NONE;
290 icr.trigger_mode = TRIGMOD_LEVEL;
291 l_apic[ICRlo] = icr.lo;
292 delay(200);
293 }
294 }
295
296 return apic_poll_errors();
297}
298
299/** Initialize Local APIC. */
300void l_apic_init(void)
301{
302 lvt_error_t error;
303 lvt_lint_t lint;
304 svr_t svr;
305 icr_t icr;
306 tdcr_t tdcr;
307 lvt_tm_t tm;
308 __u32 t1, t2;
309
310 /* Initialize LVT Error register. */
311 error.value = l_apic[LVT_Err];
312 error.masked = true;
313 l_apic[LVT_Err] = error.value;
314
315 /* Initialize LVT LINT0 register. */
316 lint.value = l_apic[LVT_LINT0];
317 lint.masked = true;
318 l_apic[LVT_LINT0] = lint.value;
319
320 /* Initialize LVT LINT1 register. */
321 lint.value = l_apic[LVT_LINT1];
322 lint.masked = true;
323 l_apic[LVT_LINT1] = lint.value;
324
325 /* Spurious-Interrupt Vector Register initialization. */
326 svr.value = l_apic[SVR];
327 svr.vector = VECTOR_APIC_SPUR;
328 svr.lapic_enabled = true;
329 l_apic[SVR] = svr.value;
330
331 l_apic[TPR] &= TPRClear;
332
333 if (CPU->arch.family >= 6)
334 enable_l_apic_in_msr();
335
336 /* Interrupt Command Register initialization. */
337 icr.lo = l_apic[ICRlo];
338 icr.delmod = DELMOD_INIT;
339 icr.destmod = DESTMOD_PHYS;
340 icr.level = LEVEL_DEASSERT;
341 icr.shorthand = SHORTHAND_ALL_INCL;
342 icr.trigger_mode = TRIGMOD_LEVEL;
343 l_apic[ICRlo] = icr.lo;
344
345 /* Timer Divide Configuration Register initialization. */
346 tdcr.value = l_apic[TDCR];
347 tdcr.div_value = DIVIDE_1;
348 l_apic[TDCR] = tdcr.value;
349
350 /* Program local timer. */
351 tm.value = l_apic[LVT_Tm];
352 tm.vector = VECTOR_CLK;
353 tm.mode = TIMER_PERIODIC;
354 tm.masked = false;
355 l_apic[LVT_Tm] = tm.value;
356
357 /* Measure and configure the timer to generate timer interrupt each ms. */
358 t1 = l_apic[CCRT];
359 l_apic[ICRT] = 0xffffffff;
360
361 while (l_apic[CCRT] == t1)
362 ;
363
364 t1 = l_apic[CCRT];
365 delay(1000);
366 t2 = l_apic[CCRT];
367
368 l_apic[ICRT] = t1-t2;
369}
370
371/** Local APIC End of Interrupt. */
372void l_apic_eoi(void)
373{
374 l_apic[EOI] = 0;
375}
376
377/** Dump content of Local APIC registers. */
378void l_apic_debug(void)
379{
380#ifdef LAPIC_VERBOSE
381 lvt_tm_t tm;
382 lvt_lint_t lint;
383 lvt_error_t error;
384
385 printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
386
387 tm.value = l_apic[LVT_Tm];
388 printf("LVT Tm: vector=%B, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);
389 lint.value = l_apic[LVT_LINT0];
390 printf("LVT LINT0: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
391 lint.value = l_apic[LVT_LINT1];
392 printf("LVT LINT1: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
393 error.value = l_apic[LVT_Err];
394 printf("LVT Err: vector=%B, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);
395#endif
396}
397
398/** Local APIC Timer Interrupt.
399 *
400 * @param n Interrupt vector number.
401 * @param stack Interrupted stack.
402 */
403void l_apic_timer_interrupt(__u8 n, __native stack[])
404{
405 l_apic_eoi();
406 clock();
407}
408
409/** Get Local APIC ID.
410 *
411 * @return Local APIC ID.
412 */
413__u8 l_apic_id(void)
414{
415 l_apic_id_t idreg;
416
417 idreg.value = l_apic[L_APIC_ID];
418 return idreg.apic_id;
419}
420
421/** Read from IO APIC register.
422 *
423 * @param address IO APIC register address.
424 *
425 * @return Content of the addressed IO APIC register.
426 */
427__u32 io_apic_read(__u8 address)
428{
429 io_regsel_t regsel;
430
431 regsel.value = io_apic[IOREGSEL];
432 regsel.reg_addr = address;
433 io_apic[IOREGSEL] = regsel.value;
434 return io_apic[IOWIN];
435}
436
437/** Write to IO APIC register.
438 *
439 * @param address IO APIC register address.
440 * @param Content to be written to the addressed IO APIC register.
441 */
442void io_apic_write(__u8 address, __u32 x)
443{
444 io_regsel_t regsel;
445
446 regsel.value = io_apic[IOREGSEL];
447 regsel.reg_addr = address;
448 io_apic[IOREGSEL] = regsel.value;
449 io_apic[IOWIN] = x;
450}
451
452/** Change some attributes of one item in I/O Redirection Table.
453 *
454 * @param pin IO APIC pin number.
455 * @param dest Interrupt destination address.
456 * @param v Interrupt vector to trigger.
457 * @param flags Flags.
458 */
459void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags)
460{
461 io_redirection_reg_t reg;
462 int dlvr = DELMOD_FIXED;
463
464 if (flags & LOPRI)
465 dlvr = DELMOD_LOWPRI;
466
467
468 reg.lo = io_apic_read(IOREDTBL + pin*2);
469 reg.hi = io_apic_read(IOREDTBL + pin*2 + 1);
470
471 reg.dest = dest;
472 reg.destmod = DESTMOD_LOGIC;
473 reg.trigger_mode = TRIGMOD_EDGE;
474 reg.intpol = POLARITY_HIGH;
475 reg.delmod = dlvr;
476 reg.intvec = v;
477
478 io_apic_write(IOREDTBL + pin*2, reg.lo);
479 io_apic_write(IOREDTBL + pin*2 + 1, reg.hi);
480}
481
482/** Mask IRQs in IO APIC.
483 *
484 * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask).
485 */
486void io_apic_disable_irqs(__u16 irqmask)
487{
488 io_redirection_reg_t reg;
489 int i, pin;
490
491 for (i=0;i<16;i++) {
492 if (irqmask & (1<<i)) {
493 /*
494 * Mask the signal input in IO APIC if there is a
495 * mapping for the respective IRQ number.
496 */
497 pin = smp_irq_to_pin(i);
498 if (pin != -1) {
499 reg.lo = io_apic_read(IOREDTBL + pin*2);
500 reg.masked = true;
501 io_apic_write(IOREDTBL + pin*2, reg.lo);
502 }
503
504 }
505 }
506}
507
508/** Unmask IRQs in IO APIC.
509 *
510 * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask).
511 */
512void io_apic_enable_irqs(__u16 irqmask)
513{
514 int i, pin;
515 io_redirection_reg_t reg;
516
517 for (i=0;i<16;i++) {
518 if (irqmask & (1<<i)) {
519 /*
520 * Unmask the signal input in IO APIC if there is a
521 * mapping for the respective IRQ number.
522 */
523 pin = smp_irq_to_pin(i);
524 if (pin != -1) {
525 reg.lo = io_apic_read(IOREDTBL + pin*2);
526 reg.masked = false;
527 io_apic_write(IOREDTBL + pin*2, reg.lo);
528 }
529
530 }
531 }
532}
533
534#endif /* CONFIG_SMP */
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