source: mainline/arch/ia32/src/smp/apic.c@ 78c32b4

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 78c32b4 was 78c32b4, checked in by Jakub Jermar <jakub@…>, 20 years ago

Add VMware Workstation 5.5 to SMP compatibility list.
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File size: 12.5 KB
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1/*
2 * Copyright (C) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <arch/types.h>
30#include <arch/smp/apic.h>
31#include <arch/smp/ap.h>
32#include <arch/smp/mps.h>
33#include <mm/page.h>
34#include <time/delay.h>
35#include <arch/interrupt.h>
36#include <print.h>
37#include <arch/asm.h>
38#include <arch.h>
39
40#ifdef CONFIG_SMP
41
42/*
43 * Advanced Programmable Interrupt Controller for SMP systems.
44 * Tested on:
45 * Bochs 2.0.2 - Bochs 2.2 with 2-8 CPUs
46 * Simics 2.0.28 - Simics 2.2.19 2-8 CPUs
47 * VMware Workstation 5.5 with 2 CPUs
48 * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
49 * ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
50 * MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
51 */
52
53/*
54 * These variables either stay configured as initilalized, or are changed by
55 * the MP configuration code.
56 *
57 * Pay special attention to the volatile keyword. Without it, gcc -O2 would
58 * optimize the code too much and accesses to l_apic and io_apic, that must
59 * always be 32-bit, would use byte oriented instructions.
60 */
61volatile __u32 *l_apic = (__u32 *) 0xfee00000;
62volatile __u32 *io_apic = (__u32 *) 0xfec00000;
63
64__u32 apic_id_mask = 0;
65
66static int apic_poll_errors(void);
67
68#ifdef LAPIC_VERBOSE
69static char *delmod_str[] = {
70 "Fixed",
71 "Lowest Priority",
72 "SMI",
73 "Reserved",
74 "NMI",
75 "INIT",
76 "STARTUP",
77 "ExtInt"
78};
79
80static char *destmod_str[] = {
81 "Physical",
82 "Logical"
83};
84
85static char *trigmod_str[] = {
86 "Edge",
87 "Level"
88};
89
90static char *mask_str[] = {
91 "Unmasked",
92 "Masked"
93};
94
95static char *delivs_str[] = {
96 "Idle",
97 "Send Pending"
98};
99
100static char *tm_mode_str[] = {
101 "One-shot",
102 "Periodic"
103};
104
105static char *intpol_str[] = {
106 "Polarity High",
107 "Polarity Low"
108};
109#endif /* LAPIC_VERBOSE */
110
111/** Initialize APIC on BSP. */
112void apic_init(void)
113{
114 io_apic_id_t idreg;
115 int i;
116
117 trap_register(VECTOR_APIC_SPUR, apic_spurious);
118
119 enable_irqs_function = io_apic_enable_irqs;
120 disable_irqs_function = io_apic_disable_irqs;
121 eoi_function = l_apic_eoi;
122
123 /*
124 * Configure interrupt routing.
125 * IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
126 * Other interrupts will be forwarded to the lowest priority CPU.
127 */
128 io_apic_disable_irqs(0xffff);
129 trap_register(VECTOR_CLK, l_apic_timer_interrupt);
130 for (i = 0; i < IRQ_COUNT; i++) {
131 int pin;
132
133 if ((pin = smp_irq_to_pin(i)) != -1) {
134 io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI);
135 }
136 }
137
138 /*
139 * Ensure that io_apic has unique ID.
140 */
141 idreg.value = io_apic_read(IOAPICID);
142 if ((1<<idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */
143 for (i = 0; i < APIC_ID_COUNT; i++) {
144 if (!((1<<i) & apic_id_mask)) {
145 idreg.apic_id = i;
146 io_apic_write(IOAPICID, idreg.value);
147 break;
148 }
149 }
150 }
151
152 /*
153 * Configure the BSP's lapic.
154 */
155 l_apic_init();
156
157 l_apic_debug();
158}
159
160/** APIC spurious interrupt handler.
161 *
162 * @param n Interrupt vector.
163 * @param stack Interrupted stack.
164 */
165void apic_spurious(__u8 n, __native stack[])
166{
167 printf("cpu%d: APIC spurious interrupt\n", CPU->id);
168}
169
170/** Poll for APIC errors.
171 *
172 * Examine Error Status Register and report all errors found.
173 *
174 * @return 0 on error, 1 on success.
175 */
176int apic_poll_errors(void)
177{
178 esr_t esr;
179
180 esr.value = l_apic[ESR];
181
182 if (esr.send_checksum_error)
183 printf("Send Checksum Error\n");
184 if (esr.receive_checksum_error)
185 printf("Receive Checksum Error\n");
186 if (esr.send_accept_error)
187 printf("Send Accept Error\n");
188 if (esr.receive_accept_error)
189 printf("Receive Accept Error\n");
190 if (esr.send_illegal_vector)
191 printf("Send Illegal Vector\n");
192 if (esr.received_illegal_vector)
193 printf("Received Illegal Vector\n");
194 if (esr.illegal_register_address)
195 printf("Illegal Register Address\n");
196
197 return !esr.err_bitmap;
198}
199
200/** Send all CPUs excluding CPU IPI vector.
201 *
202 * @param vector Interrupt vector to be sent.
203 *
204 * @return 0 on failure, 1 on success.
205 */
206int l_apic_broadcast_custom_ipi(__u8 vector)
207{
208 icr_t icr;
209
210 icr.lo = l_apic[ICRlo];
211 icr.delmod = DELMOD_FIXED;
212 icr.destmod = DESTMOD_LOGIC;
213 icr.level = LEVEL_ASSERT;
214 icr.shorthand = SHORTHAND_ALL_EXCL;
215 icr.trigger_mode = TRIGMOD_LEVEL;
216 icr.vector = vector;
217
218 l_apic[ICRlo] = icr.lo;
219
220 icr.lo = l_apic[ICRlo];
221 if (icr.delivs == DELIVS_PENDING)
222 printf("IPI is pending.\n");
223
224 return apic_poll_errors();
225}
226
227/** Universal Start-up Algorithm for bringing up the AP processors.
228 *
229 * @param apicid APIC ID of the processor to be brought up.
230 *
231 * @return 0 on failure, 1 on success.
232 */
233int l_apic_send_init_ipi(__u8 apicid)
234{
235 icr_t icr;
236 int i;
237
238 /*
239 * Read the ICR register in and zero all non-reserved fields.
240 */
241 icr.lo = l_apic[ICRlo];
242 icr.hi = l_apic[ICRhi];
243
244 icr.delmod = DELMOD_INIT;
245 icr.destmod = DESTMOD_PHYS;
246 icr.level = LEVEL_ASSERT;
247 icr.trigger_mode = TRIGMOD_LEVEL;
248 icr.shorthand = SHORTHAND_NONE;
249 icr.vector = 0;
250 icr.dest = apicid;
251
252 l_apic[ICRhi] = icr.hi;
253 l_apic[ICRlo] = icr.lo;
254
255 /*
256 * According to MP Specification, 20us should be enough to
257 * deliver the IPI.
258 */
259 delay(20);
260
261 if (!apic_poll_errors()) return 0;
262
263 icr.lo = l_apic[ICRlo];
264 if (icr.delivs == DELIVS_PENDING)
265 printf("IPI is pending.\n");
266
267 icr.delmod = DELMOD_INIT;
268 icr.destmod = DESTMOD_PHYS;
269 icr.level = LEVEL_DEASSERT;
270 icr.shorthand = SHORTHAND_NONE;
271 icr.trigger_mode = TRIGMOD_LEVEL;
272 icr.vector = 0;
273 l_apic[ICRlo] = icr.lo;
274
275 /*
276 * Wait 10ms as MP Specification specifies.
277 */
278 delay(10000);
279
280 if (!is_82489DX_apic(l_apic[LAVR])) {
281 /*
282 * If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
283 */
284 for (i = 0; i<2; i++) {
285 icr.lo = l_apic[ICRlo];
286 icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */
287 icr.delmod = DELMOD_STARTUP;
288 icr.destmod = DESTMOD_PHYS;
289 icr.level = LEVEL_ASSERT;
290 icr.shorthand = SHORTHAND_NONE;
291 icr.trigger_mode = TRIGMOD_LEVEL;
292 l_apic[ICRlo] = icr.lo;
293 delay(200);
294 }
295 }
296
297 return apic_poll_errors();
298}
299
300/** Initialize Local APIC. */
301void l_apic_init(void)
302{
303 lvt_error_t error;
304 lvt_lint_t lint;
305 svr_t svr;
306 icr_t icr;
307 tdcr_t tdcr;
308 lvt_tm_t tm;
309 __u32 t1, t2;
310
311 /* Initialize LVT Error register. */
312 error.value = l_apic[LVT_Err];
313 error.masked = true;
314 l_apic[LVT_Err] = error.value;
315
316 /* Initialize LVT LINT0 register. */
317 lint.value = l_apic[LVT_LINT0];
318 lint.masked = true;
319 l_apic[LVT_LINT0] = lint.value;
320
321 /* Initialize LVT LINT1 register. */
322 lint.value = l_apic[LVT_LINT1];
323 lint.masked = true;
324 l_apic[LVT_LINT1] = lint.value;
325
326 /* Spurious-Interrupt Vector Register initialization. */
327 svr.value = l_apic[SVR];
328 svr.vector = VECTOR_APIC_SPUR;
329 svr.lapic_enabled = true;
330 l_apic[SVR] = svr.value;
331
332 l_apic[TPR] &= TPRClear;
333
334 if (CPU->arch.family >= 6)
335 enable_l_apic_in_msr();
336
337 /* Interrupt Command Register initialization. */
338 icr.lo = l_apic[ICRlo];
339 icr.delmod = DELMOD_INIT;
340 icr.destmod = DESTMOD_PHYS;
341 icr.level = LEVEL_DEASSERT;
342 icr.shorthand = SHORTHAND_ALL_INCL;
343 icr.trigger_mode = TRIGMOD_LEVEL;
344 l_apic[ICRlo] = icr.lo;
345
346 /* Timer Divide Configuration Register initialization. */
347 tdcr.value = l_apic[TDCR];
348 tdcr.div_value = DIVIDE_1;
349 l_apic[TDCR] = tdcr.value;
350
351 /* Program local timer. */
352 tm.value = l_apic[LVT_Tm];
353 tm.vector = VECTOR_CLK;
354 tm.mode = TIMER_PERIODIC;
355 tm.masked = false;
356 l_apic[LVT_Tm] = tm.value;
357
358 /* Measure and configure the timer to generate timer interrupt each ms. */
359 t1 = l_apic[CCRT];
360 l_apic[ICRT] = 0xffffffff;
361
362 while (l_apic[CCRT] == t1)
363 ;
364
365 t1 = l_apic[CCRT];
366 delay(1000);
367 t2 = l_apic[CCRT];
368
369 l_apic[ICRT] = t1-t2;
370}
371
372/** Local APIC End of Interrupt. */
373void l_apic_eoi(void)
374{
375 l_apic[EOI] = 0;
376}
377
378/** Dump content of Local APIC registers. */
379void l_apic_debug(void)
380{
381#ifdef LAPIC_VERBOSE
382 lvt_tm_t tm;
383 lvt_lint_t lint;
384 lvt_error_t error;
385
386 printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
387
388 tm.value = l_apic[LVT_Tm];
389 printf("LVT Tm: vector=%B, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);
390 lint.value = l_apic[LVT_LINT0];
391 printf("LVT LINT0: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
392 lint.value = l_apic[LVT_LINT1];
393 printf("LVT LINT1: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
394 error.value = l_apic[LVT_Err];
395 printf("LVT Err: vector=%B, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);
396#endif
397}
398
399/** Local APIC Timer Interrupt.
400 *
401 * @param n Interrupt vector number.
402 * @param stack Interrupted stack.
403 */
404void l_apic_timer_interrupt(__u8 n, __native stack[])
405{
406 l_apic_eoi();
407 clock();
408}
409
410/** Get Local APIC ID.
411 *
412 * @return Local APIC ID.
413 */
414__u8 l_apic_id(void)
415{
416 l_apic_id_t idreg;
417
418 idreg.value = l_apic[L_APIC_ID];
419 return idreg.apic_id;
420}
421
422/** Read from IO APIC register.
423 *
424 * @param address IO APIC register address.
425 *
426 * @return Content of the addressed IO APIC register.
427 */
428__u32 io_apic_read(__u8 address)
429{
430 io_regsel_t regsel;
431
432 regsel.value = io_apic[IOREGSEL];
433 regsel.reg_addr = address;
434 io_apic[IOREGSEL] = regsel.value;
435 return io_apic[IOWIN];
436}
437
438/** Write to IO APIC register.
439 *
440 * @param address IO APIC register address.
441 * @param Content to be written to the addressed IO APIC register.
442 */
443void io_apic_write(__u8 address, __u32 x)
444{
445 io_regsel_t regsel;
446
447 regsel.value = io_apic[IOREGSEL];
448 regsel.reg_addr = address;
449 io_apic[IOREGSEL] = regsel.value;
450 io_apic[IOWIN] = x;
451}
452
453/** Change some attributes of one item in I/O Redirection Table.
454 *
455 * @param pin IO APIC pin number.
456 * @param dest Interrupt destination address.
457 * @param v Interrupt vector to trigger.
458 * @param flags Flags.
459 */
460void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags)
461{
462 io_redirection_reg_t reg;
463 int dlvr = DELMOD_FIXED;
464
465 if (flags & LOPRI)
466 dlvr = DELMOD_LOWPRI;
467
468
469 reg.lo = io_apic_read(IOREDTBL + pin*2);
470 reg.hi = io_apic_read(IOREDTBL + pin*2 + 1);
471
472 reg.dest = dest;
473 reg.destmod = DESTMOD_LOGIC;
474 reg.trigger_mode = TRIGMOD_EDGE;
475 reg.intpol = POLARITY_HIGH;
476 reg.delmod = dlvr;
477 reg.intvec = v;
478
479 io_apic_write(IOREDTBL + pin*2, reg.lo);
480 io_apic_write(IOREDTBL + pin*2 + 1, reg.hi);
481}
482
483/** Mask IRQs in IO APIC.
484 *
485 * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask).
486 */
487void io_apic_disable_irqs(__u16 irqmask)
488{
489 io_redirection_reg_t reg;
490 int i, pin;
491
492 for (i=0;i<16;i++) {
493 if (irqmask & (1<<i)) {
494 /*
495 * Mask the signal input in IO APIC if there is a
496 * mapping for the respective IRQ number.
497 */
498 pin = smp_irq_to_pin(i);
499 if (pin != -1) {
500 reg.lo = io_apic_read(IOREDTBL + pin*2);
501 reg.masked = true;
502 io_apic_write(IOREDTBL + pin*2, reg.lo);
503 }
504
505 }
506 }
507}
508
509/** Unmask IRQs in IO APIC.
510 *
511 * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask).
512 */
513void io_apic_enable_irqs(__u16 irqmask)
514{
515 int i, pin;
516 io_redirection_reg_t reg;
517
518 for (i=0;i<16;i++) {
519 if (irqmask & (1<<i)) {
520 /*
521 * Unmask the signal input in IO APIC if there is a
522 * mapping for the respective IRQ number.
523 */
524 pin = smp_irq_to_pin(i);
525 if (pin != -1) {
526 reg.lo = io_apic_read(IOREDTBL + pin*2);
527 reg.masked = false;
528 io_apic_write(IOREDTBL + pin*2, reg.lo);
529 }
530
531 }
532 }
533}
534
535#endif /* CONFIG_SMP */
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