source: mainline/arch/ia32/src/cpu/cpu.c@ 6bcf7d4

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 6bcf7d4 was f761f1eb, checked in by Jakub Jermar <jakub@…>, 20 years ago

Initial import

  • Property mode set to 100644
File size: 3.0 KB
Line 
1/*
2 * Copyright (C) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <arch/cpu.h>
30#include <arch/cpuid.h>
31#include <arch/pm.h>
32
33#include <arch.h>
34#include <arch/types.h>
35#include <print.h>
36#include <typedefs.h>
37
38/*
39 * Identification of CPUs.
40 * Contains only non-MP-Specification specific SMP code.
41 */
42#define AMD_CPUID_EBX 0x68747541
43#define AMD_CPUID_ECX 0x444d4163
44#define AMD_CPUID_EDX 0x69746e65
45
46#define INTEL_CPUID_EBX 0x756e6547
47#define INTEL_CPUID_ECX 0x6c65746e
48#define INTEL_CPUID_EDX 0x49656e69
49
50enum vendor {
51 VendorUnknown=0,
52 VendorAMD,
53 VendorIntel
54};
55
56static char *vendor_str[] = {
57 "Unknown Vendor",
58 "AuthenticAMD",
59 "GenuineIntel"
60};
61
62void cpu_arch_init(void)
63{
64 the->cpu->arch.tss = tss_p;
65}
66
67
68void cpu_identify(void)
69{
70 cpu_info_t info;
71 int i;
72
73 the->cpu->arch.vendor = VendorUnknown;
74 if (has_cpuid()) {
75 cpuid(0, &info);
76
77 /*
78 * Check for AMD processor.
79 */
80 if (info.cpuid_ebx==AMD_CPUID_EBX &&
81 info.cpuid_ecx==AMD_CPUID_ECX &&
82 info.cpuid_edx==AMD_CPUID_EDX) {
83
84 the->cpu->arch.vendor = VendorAMD;
85 }
86
87 /*
88 * Check for Intel processor.
89 */
90 if (info.cpuid_ebx==INTEL_CPUID_EBX &&
91 info.cpuid_ecx==INTEL_CPUID_ECX &&
92 info.cpuid_edx==INTEL_CPUID_EDX) {
93
94 the->cpu->arch.vendor = VendorIntel;
95
96 }
97
98 cpuid(1, &info);
99 the->cpu->arch.family = (info.cpuid_eax>>8)&0xf;
100 the->cpu->arch.model = (info.cpuid_eax>>4)&0xf;
101 the->cpu->arch.stepping = (info.cpuid_eax>>0)&0xf;
102 }
103}
104
105void cpu_print_report(struct cpu* m)
106{
107 printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n",
108 m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model, m->arch.stepping,
109 m->frequency_mhz);
110}
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