source: mainline/arch/ia32/include/smp/apic.h@ 78c32b4

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 78c32b4 was 9149135, checked in by Jakub Jermar <jakub@…>, 20 years ago

SMP cleanup continued.
Add nice type for IO APIC ID register.
Replace some magic numbers with more descriptive macros.
  • Property mode set to 100644
File size: 9.1 KB
Line 
1/*
2 * Copyright (C) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __APIC_H__
30#define __APIC_H__
31
32#include <arch/types.h>
33#include <cpu.h>
34
35#define FIXED (0<<0)
36#define LOPRI (1<<0)
37
38#define APIC_ID_COUNT 16
39
40/* local APIC macros */
41#define IPI_INIT 0
42#define IPI_STARTUP 0
43
44/** Delivery modes. */
45#define DELMOD_FIXED 0x0
46#define DELMOD_LOWPRI 0x1
47#define DELMOD_SMI 0x2
48/* 0x3 reserved */
49#define DELMOD_NMI 0x4
50#define DELMOD_INIT 0x5
51#define DELMOD_STARTUP 0x6
52#define DELMOD_EXTINT 0x7
53
54/** Destination modes. */
55#define DESTMOD_PHYS 0x0
56#define DESTMOD_LOGIC 0x1
57
58/** Trigger Modes. */
59#define TRIGMOD_EDGE 0x0
60#define TRIGMOD_LEVEL 0x1
61
62/** Levels. */
63#define LEVEL_DEASSERT 0x0
64#define LEVEL_ASSERT 0x1
65
66/** Destination Shorthands. */
67#define SHORTHAND_NONE 0x0
68#define SHORTHAND_SELF 0x1
69#define SHORTHAND_ALL_INCL 0x2
70#define SHORTHAND_ALL_EXCL 0x3
71
72/** Interrupt Input Pin Polarities. */
73#define POLARITY_HIGH 0x0
74#define POLARITY_LOW 0x1
75
76/** Divide Values. (Bit 2 is always 0) */
77#define DIVIDE_2 0x0
78#define DIVIDE_4 0x1
79#define DIVIDE_8 0x2
80#define DIVIDE_16 0x3
81#define DIVIDE_32 0x8
82#define DIVIDE_64 0x9
83#define DIVIDE_128 0xa
84#define DIVIDE_1 0xb
85
86/** Timer Modes. */
87#define TIMER_ONESHOT 0x0
88#define TIMER_PERIODIC 0x1
89
90/** Delivery status. */
91#define DELIVS_IDLE 0x0
92#define DELIVS_PENDING 0x1
93
94/** Destination masks. */
95#define DEST_ALL 0xff
96
97/** Interrupt Command Register. */
98#define ICRlo (0x300/sizeof(__u32))
99#define ICRhi (0x310/sizeof(__u32))
100struct icr {
101 union {
102 __u32 lo;
103 struct {
104 __u8 vector; /**< Interrupt Vector. */
105 unsigned delmod : 3; /**< Delivery Mode. */
106 unsigned destmod : 1; /**< Destination Mode. */
107 unsigned delivs : 1; /**< Delivery status (RO). */
108 unsigned : 1; /**< Reserved. */
109 unsigned level : 1; /**< Level. */
110 unsigned trigger_mode : 1; /**< Trigger Mode. */
111 unsigned : 2; /**< Reserved. */
112 unsigned shorthand : 2; /**< Destination Shorthand. */
113 unsigned : 12; /**< Reserved. */
114 } __attribute__ ((packed));
115 };
116 union {
117 __u32 hi;
118 struct {
119 unsigned : 24; /**< Reserved. */
120 __u8 dest; /**< Destination field. */
121 } __attribute__ ((packed));
122 };
123} __attribute__ ((packed));
124typedef struct icr icr_t;
125
126/* End Of Interrupt */
127#define EOI (0x0b0/sizeof(__u32))
128
129/** Error Status Register. */
130#define ESR (0x280/sizeof(__u32))
131union esr {
132 __u32 value;
133 __u8 err_bitmap;
134 struct {
135 unsigned send_checksum_error : 1;
136 unsigned receive_checksum_error : 1;
137 unsigned send_accept_error : 1;
138 unsigned receive_accept_error : 1;
139 unsigned : 1;
140 unsigned send_illegal_vector : 1;
141 unsigned received_illegal_vector : 1;
142 unsigned illegal_register_address : 1;
143 unsigned : 24;
144 } __attribute__ ((packed));
145};
146typedef union esr esr_t;
147
148/* Task Priority Register */
149#define TPR (0x080/sizeof(__u32))
150#define TPRClear 0xffffff00
151
152/** Spurious-Interrupt Vector Register. */
153#define SVR (0x0f0/sizeof(__u32))
154union svr {
155 __u32 value;
156 struct {
157 __u8 vector; /**< Spurious Vector */
158 unsigned lapic_enabled : 1; /**< APIC Software Enable/Disable */
159 unsigned focus_checking : 1; /**< Focus Processor Checking */
160 unsigned : 22; /**< Reserved. */
161 } __attribute__ ((packed));
162};
163typedef union svr svr_t;
164
165/** Time Divide Configuration Register. */
166#define TDCR (0x3e0/sizeof(__u32))
167union tdcr {
168 __u32 value;
169 struct {
170 unsigned div_value : 4; /**< Divide Value, bit 2 is always 0. */
171 unsigned : 28; /**< Reserved. */
172 } __attribute__ ((packed));
173};
174typedef union tdcr tdcr_t;
175
176/* Initial Count Register for Timer */
177#define ICRT (0x380/sizeof(__u32))
178
179/* Current Count Register for Timer */
180#define CCRT (0x390/sizeof(__u32))
181
182/** LVT Timer register. */
183#define LVT_Tm (0x320/sizeof(__u32))
184union lvt_tm {
185 __u32 value;
186 struct {
187 __u8 vector; /**< Local Timer Interrupt vector. */
188 unsigned : 4; /**< Reserved. */
189 unsigned delivs : 1; /**< Delivery status (RO). */
190 unsigned : 3; /**< Reserved. */
191 unsigned masked : 1; /**< Interrupt Mask. */
192 unsigned mode : 1; /**< Timer Mode. */
193 unsigned : 14; /**< Reserved. */
194 } __attribute__ ((packed));
195};
196typedef union lvt_tm lvt_tm_t;
197
198/** LVT LINT registers. */
199#define LVT_LINT0 (0x350/sizeof(__u32))
200#define LVT_LINT1 (0x360/sizeof(__u32))
201union lvt_lint {
202 __u32 value;
203 struct {
204 __u8 vector; /**< LINT Interrupt vector. */
205 unsigned delmod : 3; /**< Delivery Mode. */
206 unsigned : 1; /**< Reserved. */
207 unsigned delivs : 1; /**< Delivery status (RO). */
208 unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */
209 unsigned irr : 1; /**< Remote IRR (RO). */
210 unsigned trigger_mode : 1; /**< Trigger Mode. */
211 unsigned masked : 1; /**< Interrupt Mask. */
212 unsigned : 15; /**< Reserved. */
213 } __attribute__ ((packed));
214};
215typedef union lvt_lint lvt_lint_t;
216
217/** LVT Error register. */
218#define LVT_Err (0x370/sizeof(__u32))
219union lvt_error {
220 __u32 value;
221 struct {
222 __u8 vector; /**< Local Timer Interrupt vector. */
223 unsigned : 4; /**< Reserved. */
224 unsigned delivs : 1; /**< Delivery status (RO). */
225 unsigned : 3; /**< Reserved. */
226 unsigned masked : 1; /**< Interrupt Mask. */
227 unsigned : 15; /**< Reserved. */
228 } __attribute__ ((packed));
229};
230typedef union lvt_error lvt_error_t;
231
232/** Local APIC ID Register. */
233#define L_APIC_ID (0x020/sizeof(__u32))
234union l_apic_id {
235 __u32 value;
236 struct {
237 unsigned : 24; /**< Reserved. */
238 __u8 apic_id; /**< Local APIC ID. */
239 } __attribute__ ((packed));
240};
241typedef union l_apic_id l_apic_id_t;
242
243/* Local APIC Version Register */
244#define LAVR (0x030/sizeof(__u32))
245#define LAVR_Mask 0xff
246#define is_local_apic(x) (((x)&LAVR_Mask&0xf0)==0x1)
247#define is_82489DX_apic(x) ((((x)&LAVR_Mask&0xf0)==0x0))
248#define is_local_xapic(x) (((x)&LAVR_Mask)==0x14)
249
250/* IO APIC */
251#define IOREGSEL (0x00/sizeof(__u32))
252#define IOWIN (0x10/sizeof(__u32))
253
254#define IOAPICID 0x00
255#define IOAPICVER 0x01
256#define IOAPICARB 0x02
257#define IOREDTBL 0x10
258
259/** I/O Register Select Register. */
260union io_regsel {
261 __u32 value;
262 struct {
263 __u8 reg_addr; /**< APIC Register Address. */
264 unsigned : 24; /**< Reserved. */
265 } __attribute__ ((packed));
266};
267typedef union io_regsel io_regsel_t;
268
269/** I/O Redirection Register. */
270struct io_redirection_reg {
271 union {
272 __u32 lo;
273 struct {
274 __u8 intvec; /**< Interrupt Vector. */
275 unsigned delmod : 3; /**< Delivery Mode. */
276 unsigned destmod : 1; /**< Destination mode. */
277 unsigned delivs : 1; /**< Delivery status (RO). */
278 unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */
279 unsigned irr : 1; /**< Remote IRR (RO). */
280 unsigned trigger_mode : 1; /**< Trigger Mode. */
281 unsigned masked : 1; /**< Interrupt Mask. */
282 unsigned : 15; /**< Reserved. */
283 } __attribute__ ((packed));
284 };
285 union {
286 __u32 hi;
287 struct {
288 unsigned : 24; /**< Reserved. */
289 __u8 dest : 8; /**< Destination Field. */
290 } __attribute__ ((packed));
291 };
292
293} __attribute__ ((packed));
294typedef struct io_redirection_reg io_redirection_reg_t;
295
296
297/** IO APIC Identification Register. */
298union io_apic_id {
299 __u32 value;
300 struct {
301 unsigned : 24; /**< Reserved. */
302 unsigned apic_id : 4; /**< IO APIC ID. */
303 unsigned : 4; /**< Reserved. */
304 } __attribute__ ((packed));
305};
306typedef union io_apic_id io_apic_id_t;
307
308extern volatile __u32 *l_apic;
309extern volatile __u32 *io_apic;
310
311extern __u32 apic_id_mask;
312
313extern void apic_init(void);
314extern void apic_spurious(__u8 n, __native stack[]);
315
316extern void l_apic_init(void);
317extern void l_apic_eoi(void);
318extern int l_apic_broadcast_custom_ipi(__u8 vector);
319extern int l_apic_send_init_ipi(__u8 apicid);
320extern void l_apic_debug(void);
321extern void l_apic_timer_interrupt(__u8 n, __native stack[]);
322extern __u8 l_apic_id(void);
323
324extern __u32 io_apic_read(__u8 address);
325extern void io_apic_write(__u8 address , __u32 x);
326extern void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags);
327extern void io_apic_disable_irqs(__u16 irqmask);
328extern void io_apic_enable_irqs(__u16 irqmask);
329
330#endif
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