[1141c1a] | 1 | /*
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[e515167d] | 2 | * Copyright (C) 2005 Ondrej Palkovsky
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[1141c1a] | 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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[e515167d] | 29 | #include <proc/scheduler.h>
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| 30 | #include <cpu.h>
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[39cea6a] | 31 | #include <proc/task.h>
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[e515167d] | 32 | #include <proc/thread.h>
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| 33 | #include <arch.h>
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| 34 | #include <arch/context.h> /* SP_DELTA */
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[37b451f7] | 35 | #include <arch/asm.h>
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[4e49572] | 36 | #include <arch/debugger.h>
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[6c6a19e6] | 37 | #include <print.h>
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[39cea6a] | 38 | #include <arch/pm.h>
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[9fa16b20] | 39 | #include <adt/bitmap.h>
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[23684b7] | 40 |
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[9c1ecf9] | 41 | /** Perform amd64 specific tasks needed before the new task is run.
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| 42 | *
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| 43 | * Interrupts are disabled.
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| 44 | */
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[39cea6a] | 45 | void before_task_runs_arch(void)
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[1141c1a] | 46 | {
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[9fa16b20] | 47 | count_t bits;
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[39cea6a] | 48 | ptr_16_64_t cpugdtr;
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| 49 | descriptor_t *gdt_p;
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[69a5600] | 50 | tss_descriptor_t *tss_desc;
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[39cea6a] | 51 |
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| 52 | /*
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| 53 | * Switch the I/O Permission Bitmap, if necessary.
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| 54 | */
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[9c1ecf9] | 55 |
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| 56 | /* First, copy the I/O Permission Bitmap. */
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[39cea6a] | 57 | spinlock_lock(&TASK->lock);
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[9fa16b20] | 58 | if ((bits = TASK->arch.iomap.bits)) {
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| 59 | bitmap_t iomap;
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| 60 |
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| 61 | ASSERT(TASK->arch.iomap.map);
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| 62 | bitmap_initialize(&iomap, CPU->arch.tss->iomap, TSS_IOMAP_SIZE * 8);
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| 63 | bitmap_copy(&iomap, &TASK->arch.iomap, TASK->arch.iomap.bits);
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| 64 | /*
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[69a5600] | 65 | * It is safe to set the trailing eight bits because of the extra
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[9fa16b20] | 66 | * convenience byte in TSS_IOMAP_SIZE.
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| 67 | */
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[69a5600] | 68 | bitmap_set_range(&iomap, TASK->arch.iomap.bits, 8);
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[39cea6a] | 69 | }
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| 70 | spinlock_unlock(&TASK->lock);
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| 71 |
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| 72 | /* Second, adjust TSS segment limit. */
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| 73 | gdtr_store(&cpugdtr);
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| 74 | gdt_p = (descriptor_t *) cpugdtr.base;
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[9fa16b20] | 75 | gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE + BITS2BYTES(bits) - 1);
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[39cea6a] | 76 | gdtr_load(&cpugdtr);
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[69a5600] | 77 |
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| 78 | /*
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| 79 | * Before we load new TSS limit, the current TSS descriptor
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| 80 | * type must be changed to describe inactive TSS.
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| 81 | */
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| 82 | tss_desc = (tss_descriptor_t *) &gdt_p[TSS_DES];
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| 83 | tss_desc->type = AR_TSS;
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| 84 | tr_load(gdtselector(TSS_DES));
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[9c1ecf9] | 85 | }
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| 86 |
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| 87 | /** Perform amd64 specific tasks needed before the new thread is scheduled. */
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| 88 | void before_thread_runs_arch(void)
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| 89 | {
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| 90 | CPU->arch.tss->rsp0 = (__address) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA];
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| 91 |
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| 92 | /* Syscall support - write address of thread stack pointer to
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| 93 | * hidden part of gs */
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| 94 | swapgs();
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| 95 | write_msr(AMD_MSR_GS, (__u64)&THREAD->kstack);
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| 96 | swapgs();
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| 97 |
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| 98 | /* TLS support - set FS to thread local storage */
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| 99 | write_msr(AMD_MSR_FS, THREAD->arch.tls);
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[39cea6a] | 100 |
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[4e49572] | 101 | #ifdef CONFIG_DEBUG_AS_WATCHPOINT
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| 102 | /* Set watchpoint on AS to ensure that nobody sets it to zero */
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[6c6a19e6] | 103 | if (CPU->id < BKPOINTS_MAX)
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| 104 | breakpoint_add(&((the_t *) THREAD->kstack)->as,
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| 105 | BKPOINT_WRITE | BKPOINT_CHECK_ZERO,
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| 106 | CPU->id);
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[4e49572] | 107 | #endif
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[1141c1a] | 108 | }
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[97f1691] | 109 |
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| 110 | void after_thread_ran_arch(void)
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| 111 | {
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| 112 | }
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