source: mainline/arch/amd64/src/proc/scheduler.c@ 69a5600

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 69a5600 was 69a5600, checked in by Jakub Jermar <jakub@…>, 19 years ago

I/O Permission bitmap fixes. The trailing all-one sequence must be 8 bits long.
Update TSS limit in a proper way.

  • Property mode set to 100644
File size: 3.7 KB
RevLine 
[1141c1a]1/*
[e515167d]2 * Copyright (C) 2005 Ondrej Palkovsky
[1141c1a]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[e515167d]29#include <proc/scheduler.h>
30#include <cpu.h>
[39cea6a]31#include <proc/task.h>
[e515167d]32#include <proc/thread.h>
33#include <arch.h>
34#include <arch/context.h> /* SP_DELTA */
[37b451f7]35#include <arch/asm.h>
[4e49572]36#include <arch/debugger.h>
[6c6a19e6]37#include <print.h>
[39cea6a]38#include <arch/pm.h>
[9fa16b20]39#include <adt/bitmap.h>
[23684b7]40
[9c1ecf9]41/** Perform amd64 specific tasks needed before the new task is run.
42 *
43 * Interrupts are disabled.
44 */
[39cea6a]45void before_task_runs_arch(void)
[1141c1a]46{
[9fa16b20]47 count_t bits;
[39cea6a]48 ptr_16_64_t cpugdtr;
49 descriptor_t *gdt_p;
[69a5600]50 tss_descriptor_t *tss_desc;
[39cea6a]51
52 /*
53 * Switch the I/O Permission Bitmap, if necessary.
54 */
[9c1ecf9]55
56 /* First, copy the I/O Permission Bitmap. */
[39cea6a]57 spinlock_lock(&TASK->lock);
[9fa16b20]58 if ((bits = TASK->arch.iomap.bits)) {
59 bitmap_t iomap;
60
61 ASSERT(TASK->arch.iomap.map);
62 bitmap_initialize(&iomap, CPU->arch.tss->iomap, TSS_IOMAP_SIZE * 8);
63 bitmap_copy(&iomap, &TASK->arch.iomap, TASK->arch.iomap.bits);
64 /*
[69a5600]65 * It is safe to set the trailing eight bits because of the extra
[9fa16b20]66 * convenience byte in TSS_IOMAP_SIZE.
67 */
[69a5600]68 bitmap_set_range(&iomap, TASK->arch.iomap.bits, 8);
[39cea6a]69 }
70 spinlock_unlock(&TASK->lock);
71
72 /* Second, adjust TSS segment limit. */
73 gdtr_store(&cpugdtr);
74 gdt_p = (descriptor_t *) cpugdtr.base;
[9fa16b20]75 gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE + BITS2BYTES(bits) - 1);
[39cea6a]76 gdtr_load(&cpugdtr);
[69a5600]77
78 /*
79 * Before we load new TSS limit, the current TSS descriptor
80 * type must be changed to describe inactive TSS.
81 */
82 tss_desc = (tss_descriptor_t *) &gdt_p[TSS_DES];
83 tss_desc->type = AR_TSS;
84 tr_load(gdtselector(TSS_DES));
[9c1ecf9]85}
86
87/** Perform amd64 specific tasks needed before the new thread is scheduled. */
88void before_thread_runs_arch(void)
89{
90 CPU->arch.tss->rsp0 = (__address) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA];
91
92 /* Syscall support - write address of thread stack pointer to
93 * hidden part of gs */
94 swapgs();
95 write_msr(AMD_MSR_GS, (__u64)&THREAD->kstack);
96 swapgs();
97
98 /* TLS support - set FS to thread local storage */
99 write_msr(AMD_MSR_FS, THREAD->arch.tls);
[39cea6a]100
[4e49572]101#ifdef CONFIG_DEBUG_AS_WATCHPOINT
102 /* Set watchpoint on AS to ensure that nobody sets it to zero */
[6c6a19e6]103 if (CPU->id < BKPOINTS_MAX)
104 breakpoint_add(&((the_t *) THREAD->kstack)->as,
105 BKPOINT_WRITE | BKPOINT_CHECK_ZERO,
106 CPU->id);
[4e49572]107#endif
[1141c1a]108}
[97f1691]109
110void after_thread_ran_arch(void)
111{
112}
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