[89344d85] | 1 | /*
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| 2 | * Copyright (C) 2001-2004 Jakub Jermar
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | #include <arch/cpu.h>
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| 30 | #include <arch/cpuid.h>
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| 31 | #include <arch/pm.h>
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| 32 |
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| 33 | #include <arch.h>
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| 34 | #include <arch/types.h>
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| 35 | #include <print.h>
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| 36 | #include <typedefs.h>
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[1084a784] | 37 | #include <fpu_context.h>
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[89344d85] | 38 |
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| 39 | /*
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| 40 | * Identification of CPUs.
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| 41 | * Contains only non-MP-Specification specific SMP code.
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| 42 | */
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| 43 | #define AMD_CPUID_EBX 0x68747541
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| 44 | #define AMD_CPUID_ECX 0x444d4163
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| 45 | #define AMD_CPUID_EDX 0x69746e65
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| 46 |
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| 47 | #define INTEL_CPUID_EBX 0x756e6547
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| 48 | #define INTEL_CPUID_ECX 0x6c65746e
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| 49 | #define INTEL_CPUID_EDX 0x49656e69
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| 50 |
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| 51 |
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| 52 | enum vendor {
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| 53 | VendorUnknown=0,
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| 54 | VendorAMD,
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| 55 | VendorIntel
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| 56 | };
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| 57 |
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| 58 | static char *vendor_str[] = {
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| 59 | "Unknown Vendor",
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| 60 | "AuthenticAMD",
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| 61 | "GenuineIntel"
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| 62 | };
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| 63 |
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[3396f59] | 64 |
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| 65 | /** Setup flags on processor so that we can use the FPU
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| 66 | *
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| 67 | * cr0.osfxsr = 1 -> we do support fxstor/fxrestor
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| 68 | * cr0.em = 0 -> we do not emulate coprocessor
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| 69 | * cr0.mp = 1 -> we do want lazy context switch
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| 70 | */
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| 71 | void cpu_setup_fpu(void)
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| 72 | {
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| 73 | __asm__ volatile (
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| 74 | "movq %%cr0, %%rax;"
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| 75 | "btsq $1, %%rax;" /* cr0.mp */
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| 76 | "btrq $2, %%rax;" /* cr0.em */
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| 77 | "movq %%rax, %%cr0;"
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| 78 |
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| 79 | "movq %%cr4, %%rax;"
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| 80 | "bts $9, %%rax;" /* cr4.osfxsr */
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| 81 | "movq %%rax, %%cr4;"
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| 82 | :
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| 83 | :
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| 84 | :"%rax"
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| 85 | );
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| 86 | }
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| 87 |
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| 88 | /** Set the TS flag to 1.
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| 89 | *
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| 90 | * If a thread accesses coprocessor, exception is run, which
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| 91 | * does a lazy fpu context switch.
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| 92 | *
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| 93 | */
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[b49f4ae] | 94 | void fpu_disable(void)
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[89344d85] | 95 | {
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[e515167d] | 96 | __asm__ volatile (
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[89344d85] | 97 | "mov %%cr0,%%rax;"
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[3396f59] | 98 | "bts $3,%%rax;"
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[89344d85] | 99 | "mov %%rax,%%cr0;"
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| 100 | :
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| 101 | :
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| 102 | :"%rax"
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[e515167d] | 103 | );
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[89344d85] | 104 | }
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| 105 |
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[b49f4ae] | 106 | void fpu_enable(void)
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[89344d85] | 107 | {
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[e515167d] | 108 | __asm__ volatile (
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[89344d85] | 109 | "mov %%cr0,%%rax;"
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[3396f59] | 110 | "btr $3,%%rax;"
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[89344d85] | 111 | "mov %%rax,%%cr0;"
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| 112 | :
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| 113 | :
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| 114 | :"%rax"
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[e515167d] | 115 | );
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| 116 | }
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| 117 |
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| 118 | void cpu_arch_init(void)
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| 119 | {
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| 120 | CPU->arch.tss = tss_p;
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[39cea6a] | 121 | CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] - ((__u8 *) CPU->arch.tss);
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| 122 | CPU->fpu_owner = NULL;
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[e515167d] | 123 | }
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| 124 |
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| 125 | void cpu_identify(void)
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| 126 | {
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| 127 | cpu_info_t info;
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| 128 |
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| 129 | CPU->arch.vendor = VendorUnknown;
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| 130 | if (has_cpuid()) {
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| 131 | cpuid(0, &info);
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| 132 |
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| 133 | /*
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| 134 | * Check for AMD processor.
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| 135 | */
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| 136 | if (info.cpuid_ebx==AMD_CPUID_EBX && info.cpuid_ecx==AMD_CPUID_ECX && info.cpuid_edx==AMD_CPUID_EDX) {
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| 137 | CPU->arch.vendor = VendorAMD;
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| 138 | }
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| 139 |
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| 140 | /*
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| 141 | * Check for Intel processor.
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| 142 | */
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| 143 | if (info.cpuid_ebx==INTEL_CPUID_EBX && info.cpuid_ecx==INTEL_CPUID_ECX && info.cpuid_edx==INTEL_CPUID_EDX) {
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| 144 | CPU->arch.vendor = VendorIntel;
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| 145 | }
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| 146 |
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| 147 | cpuid(1, &info);
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| 148 | CPU->arch.family = (info.cpuid_eax>>8)&0xf;
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| 149 | CPU->arch.model = (info.cpuid_eax>>4)&0xf;
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| 150 | CPU->arch.stepping = (info.cpuid_eax>>0)&0xf;
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| 151 | }
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| 152 | }
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| 153 |
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| 154 | void cpu_print_report(cpu_t* m)
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| 155 | {
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| 156 | printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n",
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| 157 | m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model, m->arch.stepping,
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| 158 | m->frequency_mhz);
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[89344d85] | 159 | }
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