Changeset f77e591d in mainline for kernel/arch/amd64/src/asm.S
- Timestamp:
- 2010-07-14T13:05:28Z (15 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 257ceb1, 4003861
- Parents:
- 2bf2e1d
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/amd64/src/asm.S
r2bf2e1d rf77e591d 192 192 #define ERROR_WORD_INTERRUPT_LIST 0x00027D00 193 193 194 #define INTERRUPT_ALIGN 256 195 196 /** Declare interrupt handlers 197 * 198 * Declare interrupt handlers for n interrupt 199 * vectors starting at vector i. 200 * 201 * The handlers call exc_dispatch(). 202 * 203 */ 204 .macro handler i n 205 194 .macro handler i 195 .global int_\i 196 int_\i: 197 206 198 /* 207 199 * Choose between version with error code and version without error 208 * code. Both versions have to be of the same size. amd64 assembly is, 209 * however, a little bit tricky. For instance, subq $0x80, %rsp and 210 * subq $0x78, %rsp can result in two instructions with different 211 * op-code lengths. 212 * Therefore we align the interrupt handlers. 200 * code. 213 201 */ 214 202 … … 290 278 addq $(ISTATE_SOFT_SIZE + 8), %rsp 291 279 iretq 292 293 .align INTERRUPT_ALIGN294 .if (\n - \i) - 1295 handler "(\i + 1)", \n296 .endif297 280 .endm 298 281 299 .align INTERRUPT_ALIGN 282 #define LIST_0_63 \ 283 0, 1, 2, 3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,\ 284 28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,\ 285 53,54,55,56,57,58,59,60,61,62,63 286 300 287 interrupt_handlers: 301 h_start: 302 handler 0 IDT_ITEMS303 h_end: 288 .irp cnt, LIST_0_63 289 handler \cnt 290 .endr 304 291 305 292 /** Low-level syscall handler … … 545 532 ret 546 533 547 .data548 .global interrupt_handler_size549 550 interrupt_handler_size: .quad (h_end - h_start) / IDT_ITEMS
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