Changeset f76fed4 in mainline for arch/amd64/src/fpu_context.c


Ignore:
Timestamp:
2006-03-03T00:20:31Z (19 years ago)
Author:
Ondrej Palkovsky <ondrap@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
09c18f7
Parents:
ddcf365
Message:

Added lazy fpu context allocation.

  • threads that don't use fpu, don't get allocated fpu context
  • fpu context alignment on AMD64 nicely disappeared
File:
1 edited

Legend:

Unmodified
Added
Removed

  • arch/amd64/src/fpu_context.c

    rddcf365 rf76fed4  
    3535void fpu_context_save(fpu_context_t *fctx)
    3636{
    37         /* Align on 16-byte boundary */
    38         if (((__u64)fctx) & 0xf)
    39                 fctx = (fpu_context_t *)((((__u64)fctx) | 0xf) + 1);
    40 
    4137        __asm__ volatile (
    4238                "fxsave %0"
    … …  
    4844void fpu_context_restore(fpu_context_t *fctx)
    4945{
    50         /* Align on 16-byte boundary */
    51         if (((__u64)fctx) & 0xf)
    52                 fctx = (fpu_context_t *)((((__u64)fctx) | 0xf) + 1);
    5346        __asm__ volatile (
    5447                "fxrstor %0"
    … …  
    5750}
    5851
    59 void fpu_init(fpu_context_t *fctx)
     52void fpu_init()
    6053{
    6154        /* TODO: Zero all SSE, MMX etc. registers */
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