Changeset f6b5593 in mainline for kernel/arch/ia64/src/mm/tlb.c
- Timestamp:
- 2009-09-21T11:53:03Z (15 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 4098e38
- Parents:
- 2f636b6 (diff), c1618ed (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the(diff)
links above to see all the changes relative to each parent. - File:
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- 1 edited
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kernel/arch/ia64/src/mm/tlb.c
r2f636b6 rf6b5593 27 27 */ 28 28 29 /** @addtogroup ia64mm 29 /** @addtogroup ia64mm 30 30 * @{ 31 31 */ … … 53 53 #include <interrupt.h> 54 54 55 #define IO_FRAME_BASE 0xFFFFC000000 56 55 57 /** Invalidate all TLB entries. */ 56 58 void tlb_invalidate_all(void) … … 59 61 uintptr_t adr; 60 62 uint32_t count1, count2, stride1, stride2; 61 63 62 64 unsigned int i, j; 63 65 64 66 adr = PAL_PTCE_INFO_BASE(); 65 67 count1 = PAL_PTCE_INFO_COUNT1(); … … 67 69 stride1 = PAL_PTCE_INFO_STRIDE1(); 68 70 stride2 = PAL_PTCE_INFO_STRIDE2(); 69 71 70 72 ipl = interrupts_disable(); 71 73 72 74 for (i = 0; i < count1; i++) { 73 75 for (j = 0; j < count2; j++) { 74 76 asm volatile ( 75 "ptc.e %0 ;;" 76 : 77 : "r" (adr) 77 "ptc.e %[adr] ;;" 78 :: [adr] "r" (adr) 78 79 ); 79 80 adr += stride2; … … 81 82 adr += stride1; 82 83 } 83 84 84 85 interrupts_restore(ipl); 85 86 86 87 srlz_d(); 87 88 srlz_i(); 89 88 90 #ifdef CONFIG_VHPT 89 91 vhpt_invalidate_all(); 90 #endif 92 #endif 91 93 } 92 94 93 95 /** Invalidate entries belonging to an address space. 94 96 * 95 * @param asid Address space identifier. 97 * @param asid Address space identifier. 98 * 96 99 */ 97 100 void tlb_invalidate_asid(asid_t asid) … … 103 106 void tlb_invalidate_pages(asid_t asid, uintptr_t page, size_t cnt) 104 107 { 105 region_register rr;108 region_register_t rr; 106 109 bool restore_rr = false; 107 110 int b = 0; 108 111 int c = cnt; 109 112 110 113 uintptr_t va; 111 114 va = page; 112 115 113 116 rr.word = rr_read(VA2VRN(va)); 114 117 if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) { … … 117 120 * Save the old content of the register and replace the RID. 118 121 */ 119 region_register rr0;120 122 region_register_t rr0; 123 121 124 rr0 = rr; 122 125 rr0.map.rid = ASID2RID(asid, VA2VRN(va)); … … 126 129 } 127 130 128 while (c >>= 1)131 while (c >>= 1) 129 132 b++; 130 133 b >>= 1; … … 169 172 break; 170 173 } 171 for(; va < (page + cnt * PAGE_SIZE); va += (1 << ps)) 172 asm volatile ("ptc.l %0, %1;;" :: "r" (va), "r" (ps << 2)); 174 175 for (; va < (page + cnt * PAGE_SIZE); va += (1 << ps)) 176 asm volatile ( 177 "ptc.l %[va], %[ps] ;;" 178 :: [va]"r" (va), 179 [ps] "r" (ps << 2) 180 ); 181 173 182 srlz_d(); 174 183 srlz_i(); … … 183 192 /** Insert data into data translation cache. 184 193 * 185 * @param va Virtual page address. 186 * @param asid Address space identifier. 187 * @param entry The rest of TLB entry as required by TLB insertion 188 * format. 194 * @param va Virtual page address. 195 * @param asid Address space identifier. 196 * @param entry The rest of TLB entry as required by TLB insertion 197 * format. 198 * 189 199 */ 190 200 void dtc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry) … … 195 205 /** Insert data into instruction translation cache. 196 206 * 197 * @param va 198 * @param asid 199 * @param entry 200 * 207 * @param va Virtual page address. 208 * @param asid Address space identifier. 209 * @param entry The rest of TLB entry as required by TLB insertion 210 * format. 201 211 */ 202 212 void itc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry) … … 207 217 /** Insert data into instruction or data translation cache. 208 218 * 209 * @param va Virtual page address. 210 * @param asid Address space identifier. 211 * @param entry The rest of TLB entry as required by TLB insertion 212 * format. 213 * @param dtc If true, insert into data translation cache, use 214 * instruction translation cache otherwise. 219 * @param va Virtual page address. 220 * @param asid Address space identifier. 221 * @param entry The rest of TLB entry as required by TLB insertion 222 * format. 223 * @param dtc If true, insert into data translation cache, use 224 * instruction translation cache otherwise. 225 * 215 226 */ 216 227 void tc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtc) 217 228 { 218 region_register rr;229 region_register_t rr; 219 230 bool restore_rr = false; 220 231 221 232 rr.word = rr_read(VA2VRN(va)); 222 233 if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) { … … 225 236 * Save the old content of the register and replace the RID. 226 237 */ 227 region_register rr0;228 238 region_register_t rr0; 239 229 240 rr0 = rr; 230 241 rr0.map.rid = ASID2RID(asid, VA2VRN(va)); … … 235 246 236 247 asm volatile ( 237 "mov r8 = psr;;\n" 238 "rsm %0;;\n" /* PSR_IC_MASK */ 239 "srlz.d;;\n" 240 "srlz.i;;\n" 241 "mov cr.ifa = %1\n" /* va */ 242 "mov cr.itir = %2;;\n" /* entry.word[1] */ 243 "cmp.eq p6,p7 = %4,r0;;\n" /* decide between itc and dtc */ 244 "(p6) itc.i %3;;\n" 245 "(p7) itc.d %3;;\n" 246 "mov psr.l = r8;;\n" 247 "srlz.d;;\n" 248 : 249 : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]), 250 "r" (entry.word[0]), "r" (dtc) 248 "mov r8 = psr ;;\n" 249 "rsm %[mask] ;;\n" /* PSR_IC_MASK */ 250 "srlz.d ;;\n" 251 "srlz.i ;;\n" 252 "mov cr.ifa = %[va]\n" /* va */ 253 "mov cr.itir = %[word1] ;;\n" /* entry.word[1] */ 254 "cmp.eq p6, p7 = %[dtc], r0 ;;\n" /* decide between itc and dtc */ 255 "(p6) itc.i %[word0] ;;\n" 256 "(p7) itc.d %[word0] ;;\n" 257 "mov psr.l = r8 ;;\n" 258 "srlz.d ;;\n" 259 :: [mask] "i" (PSR_IC_MASK), 260 [va] "r" (va), 261 [word0] "r" (entry.word[0]), 262 [word1] "r" (entry.word[1]), 263 [dtc] "r" (dtc) 251 264 : "p6", "p7", "r8" 252 265 ); … … 261 274 /** Insert data into instruction translation register. 262 275 * 263 * @param va 264 * @param asid 265 * @param entry 266 * 267 * @param tr 268 * /269 void 270 itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, size_t tr)276 * @param va Virtual page address. 277 * @param asid Address space identifier. 278 * @param entry The rest of TLB entry as required by TLB insertion 279 * format. 280 * @param tr Translation register. 281 * 282 */ 283 void itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, size_t tr) 271 284 { 272 285 tr_mapping_insert(va, asid, entry, false, tr); … … 275 288 /** Insert data into data translation register. 276 289 * 277 * @param va 278 * @param asid 279 * @param entry 280 * 281 * @param tr 282 * /283 void 284 dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, size_t tr)290 * @param va Virtual page address. 291 * @param asid Address space identifier. 292 * @param entry The rest of TLB entry as required by TLB insertion 293 * format. 294 * @param tr Translation register. 295 * 296 */ 297 void dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, size_t tr) 285 298 { 286 299 tr_mapping_insert(va, asid, entry, true, tr); … … 289 302 /** Insert data into instruction or data translation register. 290 303 * 291 * @param va 292 * @param asid 293 * @param entry 294 * 295 * @param dtr 296 * 297 * @param tr 298 * /299 void 300 tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr,304 * @param va Virtual page address. 305 * @param asid Address space identifier. 306 * @param entry The rest of TLB entry as required by TLB insertion 307 * format. 308 * @param dtr If true, insert into data translation register, use 309 * instruction translation register otherwise. 310 * @param tr Translation register. 311 * 312 */ 313 void tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr, 301 314 size_t tr) 302 315 { 303 region_register rr;316 region_register_t rr; 304 317 bool restore_rr = false; 305 318 306 319 rr.word = rr_read(VA2VRN(va)); 307 320 if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) { … … 310 323 * Save the old content of the register and replace the RID. 311 324 */ 312 region_register rr0;313 325 region_register_t rr0; 326 314 327 rr0 = rr; 315 328 rr0.map.rid = ASID2RID(asid, VA2VRN(va)); … … 318 331 srlz_i(); 319 332 } 320 333 321 334 asm volatile ( 322 "mov r8 = psr;;\n" 323 "rsm %0;;\n" /* PSR_IC_MASK */ 324 "srlz.d;;\n" 325 "srlz.i;;\n" 326 "mov cr.ifa = %1\n" /* va */ 327 "mov cr.itir = %2;;\n" /* entry.word[1] */ 328 "cmp.eq p6,p7 = %5,r0;;\n" /* decide between itr and dtr */ 329 "(p6) itr.i itr[%4] = %3;;\n" 330 "(p7) itr.d dtr[%4] = %3;;\n" 331 "mov psr.l = r8;;\n" 332 "srlz.d;;\n" 333 : 334 : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]), 335 "r" (entry.word[0]), "r" (tr), "r" (dtr) 335 "mov r8 = psr ;;\n" 336 "rsm %[mask] ;;\n" /* PSR_IC_MASK */ 337 "srlz.d ;;\n" 338 "srlz.i ;;\n" 339 "mov cr.ifa = %[va]\n" /* va */ 340 "mov cr.itir = %[word1] ;;\n" /* entry.word[1] */ 341 "cmp.eq p6, p7 = %[dtr], r0 ;;\n" /* decide between itr and dtr */ 342 "(p6) itr.i itr[%[tr]] = %[word0] ;;\n" 343 "(p7) itr.d dtr[%[tr]] = %[word0] ;;\n" 344 "mov psr.l = r8 ;;\n" 345 "srlz.d ;;\n" 346 :: [mask] "i" (PSR_IC_MASK), 347 [va] "r" (va), 348 [word1] "r" (entry.word[1]), 349 [word0] "r" (entry.word[0]), 350 [tr] "r" (tr), 351 [dtr] "r" (dtr) 336 352 : "p6", "p7", "r8" 337 353 ); … … 346 362 /** Insert data into DTLB. 347 363 * 348 * @param page 349 * @param frame 350 * @param dtr 351 * 352 * @param tr 353 * /354 void 355 dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr,364 * @param page Virtual page address including VRN bits. 365 * @param frame Physical frame address. 366 * @param dtr If true, insert into data translation register, use data 367 * translation cache otherwise. 368 * @param tr Translation register if dtr is true, ignored otherwise. 369 * 370 */ 371 void dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr, 356 372 size_t tr) 357 373 { … … 361 377 entry.word[1] = 0; 362 378 363 entry.p = true; 379 entry.p = true; /* present */ 364 380 entry.ma = MA_WRITEBACK; 365 entry.a = true; 366 entry.d = true; 381 entry.a = true; /* already accessed */ 382 entry.d = true; /* already dirty */ 367 383 entry.pl = PL_KERNEL; 368 384 entry.ar = AR_READ | AR_WRITE; … … 380 396 * Purge DTR entries used by the kernel. 381 397 * 382 * @param page Virtual page address including VRN bits. 383 * @param width Width of the purge in bits. 398 * @param page Virtual page address including VRN bits. 399 * @param width Width of the purge in bits. 400 * 384 401 */ 385 402 void dtr_purge(uintptr_t page, size_t width) 386 403 { 387 asm volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width << 2)); 404 asm volatile ( 405 "ptr.d %[page], %[width]\n" 406 :: [page] "r" (page), 407 [width] "r" (width << 2) 408 ); 388 409 } 389 410 … … 391 412 /** Copy content of PTE into data translation cache. 392 413 * 393 * @param t PTE. 414 * @param t PTE. 415 * 394 416 */ 395 417 void dtc_pte_copy(pte_t *t) 396 418 { 397 419 tlb_entry_t entry; 398 420 399 421 entry.word[0] = 0; 400 422 entry.word[1] = 0; … … 410 432 411 433 dtc_mapping_insert(t->page, t->as->asid, entry); 434 412 435 #ifdef CONFIG_VHPT 413 436 vhpt_mapping_insert(t->page, t->as->asid, entry); 414 #endif 437 #endif 415 438 } 416 439 417 440 /** Copy content of PTE into instruction translation cache. 418 441 * 419 * @param t PTE. 442 * @param t PTE. 443 * 420 444 */ 421 445 void itc_pte_copy(pte_t *t) 422 446 { 423 447 tlb_entry_t entry; 424 448 425 449 entry.word[0] = 0; 426 450 entry.word[1] = 0; … … 437 461 438 462 itc_mapping_insert(t->page, t->as->asid, entry); 463 439 464 #ifdef CONFIG_VHPT 440 465 vhpt_mapping_insert(t->page, t->as->asid, entry); 441 #endif 466 #endif 442 467 } 443 468 444 469 /** Instruction TLB fault handler for faults with VHPT turned off. 445 470 * 446 * @param vector Interruption vector. 447 * @param istate Structure with saved interruption state. 471 * @param vector Interruption vector. 472 * @param istate Structure with saved interruption state. 473 * 448 474 */ 449 475 void alternate_instruction_tlb_fault(uint64_t vector, istate_t *istate) 450 476 { 451 region_register rr;477 region_register_t rr; 452 478 rid_t rid; 453 479 uintptr_t va; 454 480 pte_t *t; 455 481 456 va = istate->cr_ifa; 482 va = istate->cr_ifa; /* faulting address */ 457 483 rr.word = rr_read(VA2VRN(va)); 458 484 rid = rr.map.rid; 459 485 460 486 page_table_lock(AS, true); 461 487 t = page_mapping_find(AS, va); … … 473 499 page_table_unlock(AS, true); 474 500 if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) { 475 fault_if_from_uspace(istate, "Page fault at %p.",va);501 fault_if_from_uspace(istate, "Page fault at %p.", va); 476 502 panic("%s: va=%p, rid=%d, iip=%p.", __func__, va, rid, 477 503 istate->cr_iip); … … 488 514 } 489 515 490 #define IO_FRAME_BASE 0xFFFFC000000491 492 516 /** 493 517 * There is special handling of memory mapped legacy io, because of 4KB sized 494 518 * access for userspace. 495 519 * 496 * @param va Virtual address of page fault. 497 * @param istate Structure with saved interruption state. 498 * 499 * @return One on success, zero on failure. 520 * @param va Virtual address of page fault. 521 * @param istate Structure with saved interruption state. 522 * 523 * @return One on success, zero on failure. 524 * 500 525 */ 501 526 static int try_memmap_io_insertion(uintptr_t va, istate_t *istate) … … 505 530 uint64_t io_page = (va & ((1 << IO_PAGE_WIDTH) - 1)) >> 506 531 USPACE_IO_PAGE_WIDTH; 507 532 508 533 if (is_io_page_accessible(io_page)) { 509 534 uint64_t page, frame; 510 535 511 536 page = IO_OFFSET + 512 537 (1 << USPACE_IO_PAGE_WIDTH) * io_page; 513 538 frame = IO_FRAME_BASE + 514 539 (1 << USPACE_IO_PAGE_WIDTH) * io_page; 515 540 516 541 tlb_entry_t entry; 517 542 518 543 entry.word[0] = 0; 519 544 entry.word[1] = 0; 520 521 entry.p = true; 522 entry.ma = MA_UNCACHEABLE; 523 entry.a = true; 524 entry.d = true; 545 546 entry.p = true; /* present */ 547 entry.ma = MA_UNCACHEABLE; 548 entry.a = true; /* already accessed */ 549 entry.d = true; /* already dirty */ 525 550 entry.pl = PL_USER; 526 551 entry.ar = AR_READ | AR_WRITE; 527 552 entry.ppn = frame >> PPN_SHIFT; 528 553 entry.ps = USPACE_IO_PAGE_WIDTH; 529 554 530 555 dtc_mapping_insert(page, TASK->as->asid, entry); 531 556 return 1; … … 536 561 } 537 562 } 538 563 539 564 return 0; 540 565 } … … 542 567 /** Data TLB fault handler for faults with VHPT turned off. 543 568 * 544 * @param vector Interruption vector. 545 * @param istate Structure with saved interruption state. 569 * @param vector Interruption vector. 570 * @param istate Structure with saved interruption state. 571 * 546 572 */ 547 573 void alternate_data_tlb_fault(uint64_t vector, istate_t *istate) 548 574 { 549 region_register rr; 550 rid_t rid; 551 uintptr_t va; 552 pte_t *t; 553 554 va = istate->cr_ifa; /* faulting address */ 555 rr.word = rr_read(VA2VRN(va)); 556 rid = rr.map.rid; 575 if (istate->cr_isr.sp) { 576 /* Speculative load. Deffer the exception 577 until a more clever approach can be used. 578 579 Currently if we try to find the mapping 580 for the speculative load while in the kernel, 581 we might introduce a livelock because of 582 the possibly invalid values of the address. */ 583 istate->cr_ipsr.ed = true; 584 return; 585 } 586 587 uintptr_t va = istate->cr_ifa; /* faulting address */ 588 589 region_register_t rr; 590 rr.word = rr_read(VA2VRN(va)); 591 rid_t rid = rr.map.rid; 557 592 if (RID2ASID(rid) == ASID_KERNEL) { 558 593 if (VA2VRN(va) == VRN_KERNEL) { … … 565 600 } 566 601 } 567 602 603 568 604 page_table_lock(AS, true); 569 t= page_mapping_find(AS, va);570 if ( t) {605 pte_t *entry = page_mapping_find(AS, va); 606 if (entry) { 571 607 /* 572 608 * The mapping was found in the software page hash table. 573 609 * Insert it into data translation cache. 574 610 */ 575 dtc_pte_copy( t);611 dtc_pte_copy(entry); 576 612 page_table_unlock(AS, true); 577 613 } else { … … 579 615 if (try_memmap_io_insertion(va, istate)) 580 616 return; 581 /* 582 * Forward the page fault to the address space page fault 617 618 /* 619 * Forward the page fault to the address space page fault 583 620 * handler. 584 621 */ 585 622 if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { 586 fault_if_from_uspace(istate, "Page fault at %p.",va);623 fault_if_from_uspace(istate, "Page fault at %p.", va); 587 624 panic("%s: va=%p, rid=%d, iip=%p.", __func__, va, rid, 588 625 istate->cr_iip); … … 595 632 * This fault should not occur. 596 633 * 597 * @param vector Interruption vector. 598 * @param istate Structure with saved interruption state. 634 * @param vector Interruption vector. 635 * @param istate Structure with saved interruption state. 636 * 599 637 */ 600 638 void data_nested_tlb_fault(uint64_t vector, istate_t *istate) 601 639 { 602 panic("%s.", __func__);640 ASSERT(false); 603 641 } 604 642 605 643 /** Data Dirty bit fault handler. 606 644 * 607 * @param vector Interruption vector. 608 * @param istate Structure with saved interruption state. 645 * @param vector Interruption vector. 646 * @param istate Structure with saved interruption state. 647 * 609 648 */ 610 649 void data_dirty_bit_fault(uint64_t vector, istate_t *istate) 611 650 { 612 region_register rr;651 region_register_t rr; 613 652 rid_t rid; 614 653 uintptr_t va; 615 654 pte_t *t; 616 655 617 va = istate->cr_ifa; 656 va = istate->cr_ifa; /* faulting address */ 618 657 rr.word = rr_read(VA2VRN(va)); 619 658 rid = rr.map.rid; 620 659 621 660 page_table_lock(AS, true); 622 661 t = page_mapping_find(AS, va); 623 ASSERT( t && t->p);624 if ( t && t->p && t->w) {662 ASSERT((t) && (t->p)); 663 if ((t) && (t->p) && (t->w)) { 625 664 /* 626 665 * Update the Dirty bit in page tables and reinsert … … 631 670 } else { 632 671 if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) { 633 fault_if_from_uspace(istate, "Page fault at %p.",va);672 fault_if_from_uspace(istate, "Page fault at %p.", va); 634 673 panic("%s: va=%p, rid=%d, iip=%p.", __func__, va, rid, 635 674 istate->cr_iip); … … 641 680 /** Instruction access bit fault handler. 642 681 * 643 * @param vector Interruption vector. 644 * @param istate Structure with saved interruption state. 682 * @param vector Interruption vector. 683 * @param istate Structure with saved interruption state. 684 * 645 685 */ 646 686 void instruction_access_bit_fault(uint64_t vector, istate_t *istate) 647 687 { 648 region_register rr;688 region_register_t rr; 649 689 rid_t rid; 650 690 uintptr_t va; 651 pte_t *t; 652 653 va = istate->cr_ifa; 691 pte_t *t; 692 693 va = istate->cr_ifa; /* faulting address */ 654 694 rr.word = rr_read(VA2VRN(va)); 655 695 rid = rr.map.rid; 656 696 657 697 page_table_lock(AS, true); 658 698 t = page_mapping_find(AS, va); 659 ASSERT( t && t->p);660 if ( t && t->p && t->x) {699 ASSERT((t) && (t->p)); 700 if ((t) && (t->p) && (t->x)) { 661 701 /* 662 702 * Update the Accessed bit in page tables and reinsert … … 679 719 * @param vector Interruption vector. 680 720 * @param istate Structure with saved interruption state. 721 * 681 722 */ 682 723 void data_access_bit_fault(uint64_t vector, istate_t *istate) 683 724 { 684 region_register rr;725 region_register_t rr; 685 726 rid_t rid; 686 727 uintptr_t va; 687 728 pte_t *t; 688 689 va = istate->cr_ifa; 729 730 va = istate->cr_ifa; /* faulting address */ 690 731 rr.word = rr_read(VA2VRN(va)); 691 732 rid = rr.map.rid; 692 733 693 734 page_table_lock(AS, true); 694 735 t = page_mapping_find(AS, va); 695 ASSERT( t && t->p);696 if ( t && t->p) {736 ASSERT((t) && (t->p)); 737 if ((t) && (t->p)) { 697 738 /* 698 739 * Update the Accessed bit in page tables and reinsert … … 715 756 * @param vector Interruption vector. 716 757 * @param istate Structure with saved interruption state. 758 * 717 759 */ 718 760 void data_access_rights_fault(uint64_t vector, istate_t *istate) 719 761 { 720 region_register rr;762 region_register_t rr; 721 763 rid_t rid; 722 764 uintptr_t va; 723 765 pte_t *t; 724 725 va = istate->cr_ifa; 766 767 va = istate->cr_ifa; /* faulting address */ 726 768 rr.word = rr_read(VA2VRN(va)); 727 769 rid = rr.map.rid; 728 770 729 771 /* 730 772 * Assume a write to a read-only page. … … 732 774 page_table_lock(AS, true); 733 775 t = page_mapping_find(AS, va); 734 ASSERT( t && t->p);776 ASSERT((t) && (t->p)); 735 777 ASSERT(!t->w); 736 778 if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) { … … 746 788 * @param vector Interruption vector. 747 789 * @param istate Structure with saved interruption state. 790 * 748 791 */ 749 792 void page_not_present(uint64_t vector, istate_t *istate) 750 793 { 751 region_register rr;794 region_register_t rr; 752 795 rid_t rid; 753 796 uintptr_t va; 754 797 pte_t *t; 755 798 756 va = istate->cr_ifa; 799 va = istate->cr_ifa; /* faulting address */ 757 800 rr.word = rr_read(VA2VRN(va)); 758 801 rid = rr.map.rid; 759 802 760 803 page_table_lock(AS, true); 761 804 t = page_mapping_find(AS, va);
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