Changeset f4c9e42 in mainline for uspace/drv/infrastructure/rootamdm37x/core_cm.h

Timestamp:

2012-10-15T18:16:25Z (13 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

52fc805

Parents:

e9d636d0

Message:

rootamdm37x: COnvert usbhost cm and core cm to new pio functions.

Fix few incorrect values.

File:

• uspace/drv/infrastructure/rootamdm37x/core_cm.h (modified) (1 diff)

uspace/drv/infrastructure/rootamdm37x/core_cm.h

@@ -156 +156 @@
         uint32_t padd4_;
         ioport32_t clksel;
-#define CORE_CM_CLKSEL_CLKSEL_L3_MASK  0x3
-#define CORE_CM_CLKSEL_CLKSEL_L3_SHIFT  0
-#define CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED1  0x1
-#define CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED2  0x2
-#define CORE_CM_CLKSEL_CLKSEL_L4_MASK  0x3
-#define CORE_CM_CLKSEL_CLKSEL_L4_SHIFT  2
-#define CORE_CM_CLKSEL_CLKSEL_L4_DIVIDED1  0x1
-#define CORE_CM_CLKSEL_CLKSEL_L4_DIVIDED2  0x2
-#define CORE_CM_CLKSEL_CLKSEL_96M_MASK  0x3
-#define CORE_CM_CLKSEL_CLKSEL_96M_SHIFT  2
-#define CORE_CM_CLKSEL_CLKSEL_96M_DIVIDED1  0x1
-#define CORE_CM_CLKSEL_CLKSEL_96M_DIVIDED2  0x2
+#define CORE_CM_CLKSEL_CLKSEL_L3_MASK  (0x3 << 0)
+#define CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED1  (0x1 << 0)
+#define CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED2  (0x2 << 0)
+#define CORE_CM_CLKSEL_CLKSEL_L4_MASK  (0x3 << 2)
+#define CORE_CM_CLKSEL_CLKSEL_L4_DIVIDED1  (0x1 << 2)
+#define CORE_CM_CLKSEL_CLKSEL_L4_DIVIDED2  (0x2 << 2)
+#define CORE_CM_CLKSEL_CLKSEL_96M_MASK  (0x3 << 12)
+#define CORE_CM_CLKSEL_CLKSEL_96M_DIVIDED1  (0x1 << 12)
+#define CORE_CM_CLKSEL_CLKSEL_96M_DIVIDED2  (0x2 << 12)
 #define CORE_CM_CLKSEL_CLKSEL_GPT10_FLAG (1 << 6)
-#define CORE_CM_CLKSEL_CLKSEL_GPT11_FLAG (1 << 6)
+#define CORE_CM_CLKSEL_CLKSEL_GPT11_FLAG (1 << 7)
 
         uint32_t padd5_;
         ioport32_t clkstctrl;
-#define CORE_CM_CLKCTRL_CLKCTRL_L3_MASK  0x3
-#define CORE_CM_CLKCTRL_CLKCTRL_L3_SHIFT  0
-#define CORE_CM_CLKCTRL_CLKCTRL_L3_AUTO_EN  0x0
-#define CORE_CM_CLKCTRL_CLKCTRL_L3_AUTO_DIS  0x3
-#define CORE_CM_CLKCTRL_CLKCTRL_L4_MASK  0x3
-#define CORE_CM_CLKCTRL_CLKCTRL_L4_SHIFT  2
-#define CORE_CM_CLKCTRL_CLKCTRL_L4_AUTO_EN  0x0
-#define CORE_CM_CLKCTRL_CLKCTRL_L4_AUTO_DIS  0x3
+#define CORE_CM_CLKCTRL_CLKCTRL_L3_MASK  (0x3 << 0)
+#define CORE_CM_CLKCTRL_CLKCTRL_L3_AUTO_EN  (0x0 << 0)
+#define CORE_CM_CLKCTRL_CLKCTRL_L3_AUTO_DIS  (0x3 << 0)
+#define CORE_CM_CLKCTRL_CLKCTRL_L4_MASK  (0x3 << 2)
+#define CORE_CM_CLKCTRL_CLKCTRL_L4_AUTO_EN  (0x0 << 2)
+#define CORE_CM_CLKCTRL_CLKCTRL_L4_AUTO_DIS  (0x3 << 2)
 
         const ioport32_t clkstst;
 #define CORE_CM_CLKSTST_CLKACTIVITY_L3_FLAG  (1 << 0)
 #define CORE_CM_CLKSTST_CLKACTIVITY_L4_FLAG  (1 << 1)
-
 } core_cm_regs_t;