Changeset eaf5e86 in mainline for uspace/drv/bus/usb/xhci/transfers.c
- Timestamp:
- 2017-10-11T13:18:54Z (8 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 63adb18
- Parents:
- ac18b08
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/bus/usb/xhci/transfers.c
rac18b08 reaf5e86 150 150 (usb_device_request_setup_packet_t*) batch->setup_buffer; 151 151 152 152 /* For the TRB formats, see xHCI specification 6.4.1.2 */ 153 153 xhci_transfer_t *transfer = xhci_transfer_alloc(batch); 154 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 155 xhci_trb_t trb_setup; 156 memset(&trb_setup, 0, sizeof(xhci_trb_t)); 157 158 TRB_CTRL_SET_SETUP_WVALUE(trb_setup, setup->value); 159 TRB_CTRL_SET_SETUP_WLENGTH(trb_setup, setup->length); 160 TRB_CTRL_SET_SETUP_WINDEX(trb_setup, setup->index); 161 TRB_CTRL_SET_SETUP_BREQ(trb_setup, setup->request); 162 TRB_CTRL_SET_SETUP_BMREQTYPE(trb_setup, setup->request_type); 163 164 /* Size of the setup packet is always 8 */ 165 TRB_CTRL_SET_XFER_LEN(trb_setup, 8); 166 // if we want an interrupt after this td is done, use 167 // TRB_CTRL_SET_IOC(trb_setup, 1); 168 169 /* Immediate data */ 170 TRB_CTRL_SET_IDT(trb_setup, 1); 171 TRB_CTRL_SET_TRB_TYPE(trb_setup, XHCI_TRB_TYPE_SETUP_STAGE); 172 TRB_CTRL_SET_TRT(trb_setup, get_transfer_type(&trb_setup, setup->request_type, setup->length)); 173 174 /* Data stage */ 175 175 xhci_trb_t trb_data; 176 176 memset(&trb_data, 0, sizeof(xhci_trb_t)); 177 177 178 179 180 181 182 183 184 185 186 187 188 189 190 178 if (setup->length > 0) { 179 trb_data.parameter = (uintptr_t) addr_to_phys(batch->buffer); 180 181 // data size (sent for OUT, or buffer size) 182 TRB_CTRL_SET_XFER_LEN(trb_data, batch->buffer_size); 183 // FIXME: TD size 4.11.2.4 184 TRB_CTRL_SET_TD_SIZE(trb_data, 1); 185 186 // if we want an interrupt after this td is done, use 187 // TRB_CTRL_SET_IOC(trb_data, 1); 188 189 // Some more fields here, no idea what they mean 190 TRB_CTRL_SET_TRB_TYPE(trb_data, XHCI_TRB_TYPE_DATA_STAGE); 191 191 192 192 transfer->direction = get_data_direction(&trb_setup, setup->request_type, setup->length); 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 193 TRB_CTRL_SET_DIR(trb_data, transfer->direction); 194 } 195 196 /* Status stage */ 197 xhci_trb_t trb_status; 198 memset(&trb_status, 0, sizeof(xhci_trb_t)); 199 200 // FIXME: Evaluate next TRB? 4.12.3 201 // TRB_CTRL_SET_ENT(trb_status, 1); 202 203 // if we want an interrupt after this td is done, use 204 TRB_CTRL_SET_IOC(trb_status, 1); 205 206 TRB_CTRL_SET_TRB_TYPE(trb_status, XHCI_TRB_TYPE_STATUS_STAGE); 207 TRB_CTRL_SET_DIR(trb_status, get_status_direction(&trb_setup, setup->request_type, setup->length)); 208 208 209 209 uintptr_t dummy = 0; 210 210 xhci_trb_ring_enqueue(ring, &trb_setup, &dummy); 211 211 if (setup->length > 0) { 212 212 xhci_trb_ring_enqueue(ring, &trb_data, &dummy); 213 213 } 214 214 xhci_trb_ring_enqueue(ring, &trb_status, &transfer->interrupt_trb_phys); 215 215 216 216 list_append(&transfer->link, &hc->transfers); 217 217 218 219 218 /* For control transfers, the target is always 1. */ 219 hc_ring_doorbell(hc, slot_id, 1); 220 220 return EOK; 221 221 } … … 236 236 237 237 // data size (sent for OUT, or buffer size) 238 239 240 238 TRB_CTRL_SET_XFER_LEN(trb, batch->buffer_size); 239 // FIXME: TD size 4.11.2.4 240 TRB_CTRL_SET_TD_SIZE(trb, 1); 241 241 242 242 // we want an interrupt after this td is done … … 245 245 TRB_CTRL_SET_TRB_TYPE(trb, XHCI_TRB_TYPE_NORMAL); 246 246 247 247 xhci_trb_ring_enqueue(ring, &trb, &transfer->interrupt_trb_phys); 248 248 list_append(&transfer->link, &hc->transfers); 249 249 250 251 250 /* For control transfers, the target is always 1. */ 251 hc_ring_doorbell(hc, slot_id, 1); 252 252 return EOK; 253 253 }
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