Changeset e84439a in mainline for arch/mips/include/context.h

Timestamp:

2005-09-06T08:51:22Z (20 years ago)

Author:

Ondrej Palkovsky <ondrap@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

e949fd6

Parents:

39ae77b

Message:

Fixed mips boot process.
On interrupt saving registers, save $lo, $hi.
Add interrupt naming to asm files (mips).
Save only necessary registers on context switch (see mips ABI).
Fixed copyright info.

File:

• arch/mips/include/context.h (modified) (2 diffs)

arch/mips/include/context.h

@@ -30 +30 @@
 #define __mips_CONTEXT_H__
 
-#include <arch/types.h>
+#define STACK_ITEM_SIZE 4
 
-#define STACK_ITEM_SIZE 4
+/* These are offsets into the register dump saved
+ * on exception entry
+ */
+#define EOFFSET_AT 0
+#define EOFFSET_V0 4
+#define EOFFSET_V1 8
+#define EOFFSET_A0 12
+#define EOFFSET_A1 16
+#define EOFFSET_A2 20
+#define EOFFSET_A3 24
+#define EOFFSET_A4 28
+#define EOFFSET_T1 32
+#define EOFFSET_T2 36
+#define EOFFSET_T3 40
+#define EOFFSET_T4 44
+#define EOFFSET_T5 48
+#define EOFFSET_T6 52
+#define EOFFSET_T7 56
+#define EOFFSET_T8 60
+#define EOFFSET_T9 64
+#define EOFFSET_S0 68
+#define EOFFSET_S1 72
+#define EOFFSET_S2 76
+#define EOFFSET_S3 80
+#define EOFFSET_S4 84
+#define EOFFSET_S5 88
+#define EOFFSET_S6 92
+#define EOFFSET_S7 96
+#define EOFFSET_S8 100
+#define EOFFSET_GP 104
+#define EOFFSET_RA 108
+#define EOFFSET_LO 112
+#define EOFFSET_HI 116
+
+#define REGISTER_SPACE 120
 
 /*
@@ -40 +74 @@
 
 
+#ifndef __ASM__
+
+#ifndef __mips_TYPES_H_
+# include <arch/types.h>
+#endif
+
+/*
+ * Only save registers that must be preserved across
+ * function calls.
+ */
 struct context {
-        __u32 r0;
-        __u32 r1;
-        __u32 r2;
-        __u32 r3;
-        __u32 r4;
-        __u32 r5;
-        __u32 r6;
-        __u32 r7;
-        __u32 r8;
-        __u32 r9;
-        __u32 r10;
-        __u32 r11;
-        __u32 r12;
-        __u32 r13;
-        __u32 r14;
-        __u32 r15;
-        __u32 r16;
-        __u32 r17;
-        __u32 r18;
-        __u32 r19;
-        __u32 r20;
-        __u32 r21;
-        __u32 r22;
-        __u32 r23;
-        __u32 r24;
-        __u32 r25;
-        __u32 r26;
-        __u32 r27;
-        __u32 r28;
         __u32 sp;
-        __u32 r30;
         __u32 pc;
+        
+        __u32 s0;
+        __u32 s1;
+        __u32 s2;
+        __u32 s3;
+        __u32 s4;
+        __u32 s5;
+        __u32 s6;
+        __u32 s7;
+        __u32 s8;
+        __u32 gp;
+
         __u32 pri;
 };
 
+#endif /* __ASM__ */
+
 #endif