Changeset ddd0499d in mainline for uspace/drv/bus/pci/pciintel/pci.c

Timestamp:

2013-09-12T22:05:13Z (12 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

4285851b

Parents:

695b6ff (diff), 7de1988c (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Support for PIO window-relative and absolute HW resource ranges.

The goal of this merge is to allow bus drivers to pass resources with IO
and memory ranges to the child drivers either in the PIO window-relative
form or system bus absolute form. Using the PIO window and the
relative/absolute attribute of a range, each driver can now reconstruct
both forms. Helper functions are provided to automate these
transformations as much as possible.

Changes in this merge in a greater detail:

• Support for PIO_WINDOW_DEV_IFACE in isa so that it can provide the PIO window to its children.

• Add 'relative' member to both hw_resource_t.res.mem_range and hw_resource_t.res.io_range so that the drivers can actually tell whether a range is absolute (eg. it was absolutized by its parent).

• Add pio_enable_resource() to allow drivers to enable PIO without the need to actually care about what kind of range the resource contains. This is used by pci now.

• Automate things even more for drivers that use hw_res_get_list_parsed(). The parsed HW resources compute both forms (relative/absolute) and offer it to the driver which is using them. Such a driver then uses whatever form is more fit for it and its purposes.

• Drivers using the parsed resources can use pio_enable_range() to enable PIO and RNGABS*()/RNGREL()/RNGSZ courtesy macros for easier access to the actual range address/size are provided.

• Device drivers affected by these API changes were converted.

• uhcirh now requires uhci to provide PIO_WINDOW_DEV_IFACE; however, the uhcirh driver is removed in the feature USB branch so there was no point in implementing this feature and UHCI USB is thus temporarily broken.

File:

• uspace/drv/bus/pci/pciintel/pci.c (modified) (7 diffs)

uspace/drv/bus/pci/pciintel/pci.c

@@ -256 +256 @@
         fibril_mutex_lock(&bus->conf_mutex);
 
-        pio_write_32(bus->conf_addr_port, host2uint32_t_le(conf_addr));
+        pio_write_32(bus->conf_addr_reg, host2uint32_t_le(conf_addr));
 
         /*
@@ -263 +263 @@
          * support shorter PIO reads offset from this register.
          */
-        val = uint32_t_le2host(pio_read_32(bus->conf_data_port));
+        val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
 
         switch (len) {
@@ -299 +299 @@
                  * missing bits first.
                  */
-                pio_write_32(bus->conf_addr_port, host2uint32_t_le(conf_addr));
-                val = uint32_t_le2host(pio_read_32(bus->conf_data_port));
+                pio_write_32(bus->conf_addr_reg, host2uint32_t_le(conf_addr));
+                val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
         }
         
@@ -317 +317 @@
         }
 
-        pio_write_32(bus->conf_addr_port, host2uint32_t_le(conf_addr));
-        pio_write_32(bus->conf_data_port, host2uint32_t_le(val));
+        pio_write_32(bus->conf_addr_reg, host2uint32_t_le(conf_addr));
+        pio_write_32(bus->conf_data_reg, host2uint32_t_le(val));
         
         fibril_mutex_unlock(&bus->conf_mutex);
@@ -449 +449 @@
                 hw_resources[count].res.io_range.address = range_addr;
                 hw_resources[count].res.io_range.size = range_size;
+                hw_resources[count].res.io_range.relative = true;
                 hw_resources[count].res.io_range.endianness = LITTLE_ENDIAN;
         } else {
@@ -454 +455 @@
                 hw_resources[count].res.mem_range.address = range_addr;
                 hw_resources[count].res.mem_range.size = range_size;
+                hw_resources[count].res.mem_range.relative = false;
                 hw_resources[count].res.mem_range.endianness = LITTLE_ENDIAN;
         }
@@ -722 +724 @@
             hw_resources.resources[1].res.io_range.address);
         
-        bus->conf_io_addr =
-            (uint32_t) hw_resources.resources[0].res.io_range.address;
-        bus->conf_io_data =
-            (uint32_t) hw_resources.resources[1].res.io_range.address;
-        
-        if (pio_enable((void *)(uintptr_t)bus->conf_io_addr, 4,
-            &bus->conf_addr_port)) {
+        if (pio_enable_resource(&bus->pio_win, &hw_resources.resources[0],
+            (void **) &bus->conf_addr_reg)) {
                 ddf_msg(LVL_ERROR, "Failed to enable configuration ports.");
                 rc = EADDRNOTAVAIL;
                 goto fail;
         }
-        if (pio_enable((void *)(uintptr_t)bus->conf_io_data, 4,
-            &bus->conf_data_port)) {
+        if (pio_enable_resource(&bus->pio_win, &hw_resources.resources[1],
+            (void **) &bus->conf_data_reg)) {
                 ddf_msg(LVL_ERROR, "Failed to enable configuration ports.");
                 rc = EADDRNOTAVAIL;