Changeset db71e2a in mainline for kernel/genarch/src/drivers/omap/uart.c

Timestamp:

2013-07-24T17:42:25Z (13 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

69b264a9

Parents:

52f1882 (diff), cffa14e6 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

merge mainline changes.

usb hc macro changes from mainline were reverted, too many conflicts

File:

• kernel/genarch/src/drivers/omap/uart.c (moved) (moved from kernel/genarch/src/drivers/amdm37x_uart/amdm37x_uart.c ) (9 diffs)

kernel/genarch/src/drivers/omap/uart.c

@@ -1 +1 @@
 /*
  * Copyright (c) 2012 Jan Vesely
+ * Copyright (c) 2013 Maurizio Lombardi
  * All rights reserved.
  *
@@ -31 +32 @@
 /**
  * @file
- * @brief Texas Instruments AMDM37x on-chip uart serial line driver.
+ * @brief Texas Instruments OMAP on-chip uart serial line driver.
  */
 
-#include <genarch/drivers/amdm37x_uart/amdm37x_uart.h>
+#include <genarch/drivers/omap/uart.h>
 #include <ddi/device.h>
 #include <str.h>
 #include <mm/km.h>
 
-static void amdm37x_uart_txb(amdm37x_uart_t *uart, uint8_t b)
+static void omap_uart_txb(omap_uart_t *uart, uint8_t b)
 {
         /* Wait for buffer */
-        while (uart->regs->ssr & AMDM37x_UART_SSR_TX_FIFO_FULL_FLAG);
+        while (uart->regs->ssr & OMAP_UART_SSR_TX_FIFO_FULL_FLAG);
         /* Write to the outgoing fifo */
         uart->regs->thr = b;
 }
 
-static void amdm37x_uart_putchar(outdev_t *dev, wchar_t ch)
+static void omap_uart_putchar(outdev_t *dev, wchar_t ch)
 {
-        amdm37x_uart_t *uart = dev->data;
+        omap_uart_t *uart = dev->data;
         if (!ascii_check(ch)) {
-                amdm37x_uart_txb(uart, U_SPECIAL);
+                omap_uart_txb(uart, U_SPECIAL);
         } else {
                 if (ch == '\n')
-                        amdm37x_uart_txb(uart, '\r');
-                amdm37x_uart_txb(uart, ch);
+                        omap_uart_txb(uart, '\r');
+                omap_uart_txb(uart, ch);
         }
 }
 
-static outdev_operations_t amdm37x_uart_ops = {
+static outdev_operations_t omap_uart_ops = {
         .redraw = NULL,
-        .write = amdm37x_uart_putchar,
+        .write = omap_uart_putchar,
 };
 
-static irq_ownership_t amdm37x_uart_claim(irq_t *irq)
+static irq_ownership_t omap_uart_claim(irq_t *irq)
 {
         return IRQ_ACCEPT;
 }
 
-static void amdm37x_uart_handler(irq_t *irq)
+static void omap_uart_handler(irq_t *irq)
 {
-        amdm37x_uart_t *uart = irq->instance;
+        omap_uart_t *uart = irq->instance;
         while ((uart->regs->rx_fifo_lvl)) {
                 const uint8_t val = uart->regs->rhr;
@@ -80 +81 @@
 }
 
-bool amdm37x_uart_init(
-    amdm37x_uart_t *uart, inr_t interrupt, uintptr_t addr, size_t size)
+bool omap_uart_init(
+    omap_uart_t *uart, inr_t interrupt, uintptr_t addr, size_t size)
 {
         ASSERT(uart);
@@ -88 +89 @@
         ASSERT(uart->regs);
 
-        /* See TI OMAP35X TRM ch 17.5.1.1 p. 2732 for startup routine */
-#if 0
         /* Soft reset the port */
-        uart->regs->sysc = AMDM37x_UART_SYSC_SOFTRESET_FLAG;
-        while (!(uart->regs->syss & AMDM37x_UART_SYSS_RESETDONE_FLAG)) ;
-#endif
+        uart->regs->sysc = OMAP_UART_SYSC_SOFTRESET_FLAG;
+        while (!(uart->regs->syss & OMAP_UART_SYSS_RESETDONE_FLAG));
+
+        /* Disable the UART module */
+        uart->regs->mdr1 |= OMAP_UART_MDR_MS_DISABLE;
 
         /* Enable access to EFR register */
-        const uint8_t lcr = uart->regs->lcr; /* Save old value */
         uart->regs->lcr = 0xbf;              /* Sets config mode B */
 
         /* Enable access to TCL_TLR register */
-        const bool enhanced = uart->regs->efr & AMDM37x_UART_EFR_ENH_FLAG;
-        uart->regs->efr |= AMDM37x_UART_EFR_ENH_FLAG; /* Turn on enh. */
+        const bool enhanced = uart->regs->efr & OMAP_UART_EFR_ENH_FLAG;
+        uart->regs->efr |= OMAP_UART_EFR_ENH_FLAG; /* Turn on enh. */
         uart->regs->lcr = 0x80;              /* Config mode A */
 
         /* Set default (val 0) triggers, disable DMA enable FIFOs */
-        const bool tcl_tlr = uart->regs->mcr & AMDM37x_UART_MCR_TCR_TLR_FLAG;
+        const bool tcl_tlr = uart->regs->mcr & OMAP_UART_MCR_TCR_TLR_FLAG;
         /* Enable access to tcr and tlr registers */
-        uart->regs->mcr |= AMDM37x_UART_MCR_TCR_TLR_FLAG;
+        uart->regs->mcr |= OMAP_UART_MCR_TCR_TLR_FLAG;
 
         /* Enable FIFOs */
-        uart->regs->fcr = AMDM37x_UART_FCR_FIFO_EN_FLAG;
+        uart->regs->fcr = OMAP_UART_FCR_FIFO_EN_FLAG;
 
-        /* Eneble fine granularity for RX FIFO and set trigger level to 1,
-         * TX FIFO, trigger level is irelevant*/
-        uart->regs->lcr = 0xbf;              /* Sets config mode B */
-        uart->regs->scr = AMDM37x_UART_SCR_RX_TRIG_GRANU1_FLAG;
-        uart->regs->tlr = 1 << AMDM37x_UART_TLR_RX_FIFO_TRIG_SHIFT;
+        /* Enable fine granularity for RX FIFO and set trigger level to 1,
+         * TX FIFO, trigger level is irrelevant*/
+        uart->regs->lcr = 0xBF;              /* Sets config mode B */
+        uart->regs->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_FLAG;
+        uart->regs->tlr = 1 << OMAP_UART_TLR_RX_FIFO_TRIG_SHIFT;
+
+        /* Sets config mode A */
+        uart->regs->lcr = 0x80;
+        /* Restore tcl_tlr access flag */
+        if (!tcl_tlr)
+                uart->regs->mcr &= ~OMAP_UART_MCR_TCR_TLR_FLAG;
+        /* Sets config mode B */
+        uart->regs->lcr = 0xBF;
+
+        /* Set the divisor value to get a baud rate of 115200 bps */
+        uart->regs->dll = 0x1A;
+        uart->regs->dlh = 0x00;
 
         /* Restore enhanced */
         if (!enhanced)
-                uart->regs->efr &= ~AMDM37x_UART_EFR_ENH_FLAG;
+                uart->regs->efr &= ~OMAP_UART_EFR_ENH_FLAG;
 
-        uart->regs->lcr = 0x80;              /* Config mode A */
-        /* Restore tcl_lcr access flag*/
-        if (!tcl_tlr)
-                uart->regs->mcr &= ~AMDM37x_UART_MCR_TCR_TLR_FLAG;
+        /* Set the DIV_EN bit to 0 */
+        uart->regs->lcr &= ~OMAP_UART_LCR_DIV_EN_FLAG;
+        /* Set the BREAK_EN bit to 0 */
+        uart->regs->lcr &= ~OMAP_UART_LCR_BREAK_EN_FLAG;
+        /* No parity */
+        uart->regs->lcr &= ~OMAP_UART_LCR_PARITY_EN_FLAG;
+        /* Stop = 1 bit */
+        uart->regs->lcr &= ~OMAP_UART_LCR_NB_STOP_FLAG;
+        /* Char length = 8 bits */
+        uart->regs->lcr |= OMAP_UART_LCR_CHAR_LENGTH_8BITS;
 
-        /* Restore lcr */
-        uart->regs->lcr = lcr;
+        /* Enable the UART module */
+        uart->regs->mdr1 &= (OMAP_UART_MDR_MS_UART16 &
+            ~OMAP_UART_MDR_MS_MASK);
 
         /* Disable interrupts */
@@ -134 +153 @@
 
         /* Setup outdev */
-        outdev_initialize("amdm37x_uart_dev", &uart->outdev, &amdm37x_uart_ops);
+        outdev_initialize("omap_uart_dev", &uart->outdev, &omap_uart_ops);
         uart->outdev.data = uart;
 
@@ -141 +160 @@
         uart->irq.devno = device_assign_devno();
         uart->irq.inr = interrupt;
-        uart->irq.claim = amdm37x_uart_claim;
-        uart->irq.handler = amdm37x_uart_handler;
+        uart->irq.claim = omap_uart_claim;
+        uart->irq.handler = omap_uart_handler;
         uart->irq.instance = uart;
 
@@ -148 +167 @@
 }
 
-void amdm37x_uart_input_wire(amdm37x_uart_t *uart, indev_t *indev)
+void omap_uart_input_wire(omap_uart_t *uart, indev_t *indev)
 {
         ASSERT(uart);
@@ -156 +175 @@
         irq_register(&uart->irq);
         /* Enable interrupt on receive */
-        uart->regs->ier |= AMDM37x_UART_IER_RHR_IRQ_FLAG;
+        uart->regs->ier |= OMAP_UART_IER_RHR_IRQ_FLAG;
 }
 
@@ -162 +181 @@
  * @}
  */
+