Changeset d6e5cbc in mainline for arch/mips32/src/interrupt.c

Timestamp:

2006-05-28T18:17:36Z (19 years ago)

Author:

Ondrej Palkovsky <ondrap@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

5552d60

Parents:

3bf5976

Message:

Added 'realtime' clock interface.
Added some asm macros as memory barriers.
Added drift computing for mips platform.

File:

• arch/mips32/src/interrupt.c (modified) (2 diffs)

arch/mips32/src/interrupt.c

@@ -77 +77 @@
 }
 
+/* TODO: This is SMP unsafe!!! */
+static unsigned long nextcount;
+/** Start hardware clock */
+static void timer_start(void)
+{
+        nextcount = cp0_compare_value + cp0_count_read();
+        cp0_compare_write(nextcount);
+}
+
 static void timer_exception(int n, istate_t *istate)
 {
-        cp0_compare_write(cp0_count_read() + cp0_compare_value); 
+        unsigned long drift;
+
+        drift = cp0_count_read() - nextcount;
+        while (drift > cp0_compare_value) {
+                drift -= cp0_compare_value;
+                CPU->missed_clock_ticks++;
+        }
+        nextcount = cp0_count_read() + cp0_compare_value - drift;
+        cp0_compare_write(nextcount);
         clock();
 }
@@ -101 +118 @@
         int_register(0, "swint0", swint0);
         int_register(1, "swint1", swint1);
+        timer_start();
 }