Changeset d5610b9 in mainline for kernel/arch/arm32/include/arch/cache.h

Timestamp:

2015-10-03T08:37:37Z (10 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

afe5e09

Parents:

8ca6f08

Message:

Cleanup some of the cache maintenance mess on ARM

• Do not define ARMv7 cache maintenance registers for ARMv6-.
• Define missing ARMv6- registers using analoguos naming convention.
• In smc_coherence() and pt_coherence_m(), do not blindly use ARMv7 DCCVMAU but decide the proper type of cache maintenance operation in dcache_clean_mva_pou().
• Also, do not use ARMv7 ICIALLU directly, but call icache_invalidate() instead, which does the right thing.

File:

• kernel/arch/arm32/include/arch/cache.h (modified) (2 diffs)

kernel/arch/arm32/include/arch/cache.h

@@ -37 +37 @@
 #define KERN_arm32_CACHE_H_
 
+#include <typedefs.h>
+
 unsigned dcache_levels(void);
 
@@ -43 +45 @@
 void cpu_dcache_flush(void);
 void cpu_dcache_flush_invalidate(void);
-void icache_invalidate(void);
+extern void icache_invalidate(void);
+extern void dcache_clean_mva_pou(uintptr_t);
 
 #endif