Changeset d53aba3f in mainline for arch/sparc64/src


Ignore:
Timestamp:
2005-12-21T23:22:38Z (20 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
096d11e5
Parents:
113b98b
Message:

sparc64 work.
Context again. It turns out, according to SCD 2.4, that registers that didn't have to be saved were saved (%o1 - %o5) and
registers that had to be saved were not saved (%i0 - %i5, %l0 - %l7).

File:
1 edited

Legend:

Unmodified
Added
Removed

  • arch/sparc64/src/context.S

    r113b98b rd53aba3f  
    4444
    4545.macro CONTEXT_STORE r
    46         stx %o1, [\r + OFFSET_O1]
    47         stx %o2, [\r + OFFSET_O2]
    48         stx %o3, [\r + OFFSET_O3]
    49         stx %o4, [\r + OFFSET_O4]
    50         stx %o5, [\r + OFFSET_O5]
     46        stx %sp, [\r + OFFSET_SP]
    5147        stx %o7, [\r + OFFSET_PC]
    52         stx %sp, [\r + OFFSET_SP]
     48        stx %i0, [\r + OFFSET_I0]
     49        stx %i1, [\r + OFFSET_I1]
     50        stx %i2, [\r + OFFSET_I2]
     51        stx %i3, [\r + OFFSET_I3]
     52        stx %i4, [\r + OFFSET_I4]
     53        stx %i5, [\r + OFFSET_I5]
    5354        stx %fp, [\r + OFFSET_FP]
    5455        stx %i7, [\r + OFFSET_I7]
     56        stx %l0, [\r + OFFSET_L0]
     57        stx %l1, [\r + OFFSET_L1]
     58        stx %l2, [\r + OFFSET_L2]
     59        stx %l3, [\r + OFFSET_L3]
     60        stx %l4, [\r + OFFSET_L4]
     61        stx %l5, [\r + OFFSET_L5]
     62        stx %l6, [\r + OFFSET_L6]
     63        stx %l7, [\r + OFFSET_L7]
    5564.endm
    5665
    5766.macro CONTEXT_LOAD r
    58         ldx [\r + OFFSET_O1], %o1
    59         ldx [\r + OFFSET_O2], %o2
    60         ldx [\r + OFFSET_O3], %o3
    61         ldx [\r + OFFSET_O4], %o4
    62         ldx [\r + OFFSET_O5], %o5
     67        ldx [\r + OFFSET_SP], %sp
    6368        ldx [\r + OFFSET_PC], %o7
    64         ldx [\r + OFFSET_SP], %sp
     69        ldx [\r + OFFSET_I0], %i0
     70        ldx [\r + OFFSET_I1], %i1
     71        ldx [\r + OFFSET_I2], %i2
     72        ldx [\r + OFFSET_I3], %i3
     73        ldx [\r + OFFSET_I4], %i4
     74        ldx [\r + OFFSET_I5], %i5
    6575        ldx [\r + OFFSET_FP], %fp
    6676        ldx [\r + OFFSET_I7], %i7
     77        ldx [\r + OFFSET_L0], %l0
     78        ldx [\r + OFFSET_L1], %l1
     79        ldx [\r + OFFSET_L2], %l2
     80        ldx [\r + OFFSET_L3], %l3
     81        ldx [\r + OFFSET_L4], %l4
     82        ldx [\r + OFFSET_L5], %l5
     83        ldx [\r + OFFSET_L6], %l6
     84        ldx [\r + OFFSET_L7], %l7
    6785.endm
    6886
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