Changeset d1582b50 in mainline for kernel/arch/arm32/src/mm/page_fault.c
- Timestamp:
- 2020-12-14T20:41:53Z (4 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 02fe42e
- Parents:
- 1382446
- git-author:
- Jiri Svoboda <jiri@…> (2020-12-14 20:33:54)
- git-committer:
- Jiri Svoboda <jiri@…> (2020-12-14 20:41:53)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/arm32/src/mm/page_fault.c
r1382446 rd1582b50 161 161 } ls_inst[] = { 162 162 /* Store word/byte */ 163 { 0x0e100000, 0x04000000, PF_ACCESS_WRITE }, /* STR(B) imm*/164 { 0x0e100010, 0x06000000, PF_ACCESS_WRITE }, /* STR(B) reg*/163 { 0x0e100000, 0x04000000, PF_ACCESS_WRITE }, /* STR(B) imm */ 164 { 0x0e100010, 0x06000000, PF_ACCESS_WRITE }, /* STR(B) reg */ 165 165 /* Load word/byte */ 166 { 0x0e100000, 0x04100000, PF_ACCESS_READ }, /* LDR(B) imm*/167 { 0x0e100010, 0x06100000, PF_ACCESS_READ }, /* LDR(B) reg*/166 { 0x0e100000, 0x04100000, PF_ACCESS_READ }, /* LDR(B) imm */ 167 { 0x0e100010, 0x06100000, PF_ACCESS_READ }, /* LDR(B) reg */ 168 168 /* Store half-word/dual A5.2.8 */ 169 { 0x0e1000b0, 0x000000b0, PF_ACCESS_WRITE }, /* STRH imm reg*/169 { 0x0e1000b0, 0x000000b0, PF_ACCESS_WRITE }, /* STRH imm reg */ 170 170 /* Load half-word/dual A5.2.8 */ 171 { 0x0e0000f0, 0x000000d0, PF_ACCESS_READ }, /* LDRH imm reg*/172 { 0x0e1000b0, 0x001000b0, PF_ACCESS_READ }, /* LDRH imm reg*/171 { 0x0e0000f0, 0x000000d0, PF_ACCESS_READ }, /* LDRH imm reg */ 172 { 0x0e1000b0, 0x001000b0, PF_ACCESS_READ }, /* LDRH imm reg */ 173 173 /* Block data transfer, Store */ 174 174 { 0x0e100000, 0x08000000, PF_ACCESS_WRITE }, /* STM variants */
Note:
See TracChangeset
for help on using the changeset viewer.