Changeset ce031f0 in mainline for arch/mips32/include/cp0.h

Timestamp:

2005-10-04T11:23:21Z (20 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

8e3f47b3

Parents:

1e2aecca

Message:

MIPS work.
Fix some name inconsistencies between cp0 functions' declarations and definitions.
Add and implement tlb_init_arch().
Add tlb_modified() exception handler.

Other architectures: add dummy tlb_init_arch().

File:

• arch/mips32/include/cp0.h (modified) (2 diffs)

arch/mips32/include/cp0.h

@@ -53 +53 @@
 #define cp0_compare_value               10000
 
-static inline void tlbp(void)
-{
-        __asm__ volatile ("tlbp");
-}
-
-static inline void tlbr(void)
-{
-        __asm__ volatile ("tlbr");
-}
-static inline void tlbwi(void)
-{
-        __asm__ volatile ("tlbwi");
-}
-static inline void tlbwr(void)
-{
-        __asm__ volatile ("tlbwr");
-}
-
 #define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))
 #define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask)
@@ -76 +58 @@
 #define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1<<(cp0_status_im_shift+(it))))
 
-
 extern  __u32 cp0_index_read(void);
-extern void cp0_idnex_write(__u32 val);
+extern void cp0_index_write(__u32 val);
 
 extern __u32 cp0_random_read(void);