Changeset ce031f0 in mainline for arch/mips32/include

Timestamp:

2005-10-04T11:23:21Z (20 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

8e3f47b3

Parents:

1e2aecca

Message:

MIPS work.
Fix some name inconsistencies between cp0 functions' declarations and definitions.
Add and implement tlb_init_arch().
Add tlb_modified() exception handler.

Other architectures: add dummy tlb_init_arch().

Location:

arch/mips32/include

Files:

• cp0.h (modified) (2 diffs)
• mm/tlb.h (modified) (2 diffs)

arch/mips32/include/cp0.h

@@ -53 +53 @@
 #define cp0_compare_value               10000
 
-static inline void tlbp(void)
-{
-        __asm__ volatile ("tlbp");
-}
-
-static inline void tlbr(void)
-{
-        __asm__ volatile ("tlbr");
-}
-static inline void tlbwi(void)
-{
-        __asm__ volatile ("tlbwi");
-}
-static inline void tlbwr(void)
-{
-        __asm__ volatile ("tlbwr");
-}
-
 #define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))
 #define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask)
@@ -76 +58 @@
 #define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1<<(cp0_status_im_shift+(it))))
 
-
 extern  __u32 cp0_index_read(void);
-extern void cp0_idnex_write(__u32 val);
+extern void cp0_index_write(__u32 val);
 
 extern __u32 cp0_random_read(void);

arch/mips32/include/mm/tlb.h

@@ -31 +31 @@
 
 #include <arch/exception.h>
+
+#define TLB_SIZE        48
+
+#define TLB_WIRED               1
+#define TLB_KSTACK_WIRED_INDEX  0
+
+#define TLB_PAGE_MASK_16K       (0x3<<13)
 
 #define PAGE_UNCACHED                   2
@@ -66 +73 @@
 typedef struct entry_lo pte_t;
 
+/** Read Indexed TLB Entry
+ *
+ * Read Indexed TLB Entry.
+ */
+static inline void tlbr(void)
+{
+        __asm__ volatile ("tlbr\n\t");
+}
+
+/** Write Indexed TLB Entry
+ *
+ * Write Indexed TLB Entry.
+ */
+static inline void tlbwi(void)
+{
+        __asm__ volatile ("tlbwi\n\t");
+}
+
+/** Write Random TLB Entry
+ *
+ * Write Random TLB Entry.
+ */
+static inline void tlbwr(void)
+{
+        __asm__ volatile ("tlbwr\n\t");
+}
+
 extern void tlb_invalid(struct exception_regdump *pstate);
 extern void tlb_refill(struct exception_regdump *pstate);
+extern void tlb_modified(struct exception_regdump *pstate);
 
 #endif