source: mainline/kernel/arch/sparc64/src/trap/interrupt.c@ d70ebffe

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since d70ebffe was d70ebffe, checked in by Jakub Jermar <jakub@…>, 11 years ago

Let the fast MMU traps use exc_dispatch() in their slow-path.

In order to get proper exception accounting, the MMU related traps need
to go through the code in exc_dispatch(). To make this possible, we pass
the DTLB Tag Access register in istate_t in order to make way for the
trap type argument, which needs to be passed as the first argument to
exc_dispatch().

As a collateral change, this commit modifies the istate_t structure to
match the SPARC V9 ABI stack frame layout. It gives us a richer istate_t
with more information in it and also simplifies calculation of stack
offsets inside of preemptible_handler.
  • Property mode set to 100644
File size: 4.5 KB
Line 
1/*
2 * Copyright (c) 2005 Jakub Jermar
3 * Copyright (c) 2009 Pavel Rimsky
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/** @addtogroup sparc64interrupt
31 * @{
32 */
33/** @file
34 */
35
36#include <arch/interrupt.h>
37#include <arch/trap/interrupt.h>
38#include <arch/trap/exception.h>
39#include <arch/trap/mmu.h>
40#include <arch/sparc64.h>
41#include <interrupt.h>
42#include <ddi/irq.h>
43#include <typedefs.h>
44#include <debug.h>
45#include <arch/asm.h>
46#include <arch/barrier.h>
47#include <arch/drivers/tick.h>
48#include <print.h>
49#include <arch.h>
50#include <mm/tlb.h>
51#include <config.h>
52#include <synch/spinlock.h>
53
54void exc_arch_init(void)
55{
56 exc_register(TT_INSTRUCTION_ACCESS_EXCEPTION,
57 "instruction_access_exception", false,
58 instruction_access_exception);
59 exc_register(TT_INSTRUCTION_ACCESS_ERROR,
60 "instruction_access_error", false,
61 instruction_access_error);
62 exc_register(TT_ILLEGAL_INSTRUCTION,
63 "illegal_instruction", false,
64 illegal_instruction);
65 exc_register(TT_PRIVILEGED_OPCODE,
66 "privileged_opcode", false,
67 privileged_opcode);
68 exc_register(TT_UNIMPLEMENTED_LDD,
69 "unimplemented_LDD", false,
70 unimplemented_LDD);
71 exc_register(TT_UNIMPLEMENTED_STD,
72 "unimplemented_STD", false,
73 unimplemented_STD);
74 exc_register(TT_FP_DISABLED,
75 "fp_disabled", true,
76 fp_disabled);
77 exc_register(TT_FP_EXCEPTION_IEEE_754,
78 "fp_exception_ieee_754", false,
79 fp_exception_ieee_754);
80 exc_register(TT_FP_EXCEPTION_OTHER,
81 "fp_exception_other", false,
82 fp_exception_other);
83 exc_register(TT_TAG_OVERFLOW,
84 "tag_overflow", false,
85 tag_overflow);
86 exc_register(TT_DIVISION_BY_ZERO,
87 "division_by_zero", false,
88 division_by_zero);
89 exc_register(TT_DATA_ACCESS_EXCEPTION,
90 "data_access_exception", false,
91 data_access_exception);
92 exc_register(TT_DATA_ACCESS_ERROR,
93 "data_access_error", false,
94 data_access_error);
95 exc_register(TT_MEM_ADDRESS_NOT_ALIGNED,
96 "mem_address_not_aligned", false,
97 mem_address_not_aligned);
98 exc_register(TT_LDDF_MEM_ADDRESS_NOT_ALIGNED,
99 "LDDF_mem_address_not_aligned", false,
100 LDDF_mem_address_not_aligned);
101 exc_register(TT_STDF_MEM_ADDRESS_NOT_ALIGNED,
102 "STDF_mem_address_not_aligned", false,
103 STDF_mem_address_not_aligned);
104 exc_register(TT_PRIVILEGED_ACTION,
105 "privileged_action", false,
106 privileged_action);
107 exc_register(TT_LDQF_MEM_ADDRESS_NOT_ALIGNED,
108 "LDQF_mem_address_not_aligned", false,
109 LDQF_mem_address_not_aligned);
110 exc_register(TT_STQF_MEM_ADDRESS_NOT_ALIGNED,
111 "STQF_mem_address_not_aligned", false,
112 STQF_mem_address_not_aligned);
113
114 exc_register(TT_INTERRUPT_LEVEL_14,
115 "interrupt_level_14", true,
116 tick_interrupt);
117
118#ifdef SUN4u
119 exc_register(TT_INTERRUPT_VECTOR_TRAP,
120 "interrupt_vector_trap", true,
121 interrupt);
122#endif
123
124 exc_register(TT_FAST_INSTRUCTION_ACCESS_MMU_MISS,
125 "fast_instruction_access_mmu_miss", true,
126 fast_instruction_access_mmu_miss);
127 exc_register(TT_FAST_DATA_ACCESS_MMU_MISS,
128 "fast_data_access_mmu_miss", true,
129 fast_data_access_mmu_miss);
130 exc_register(TT_FAST_DATA_ACCESS_PROTECTION,
131 "fast_data_access_protection", true,
132 fast_data_access_protection);
133}
134
135/** @}
136 */
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