Changeset bfa4ffa in mainline for uspace/drv/bus/pci/pciintel/pci.c


Ignore:
Timestamp:
2016-12-27T13:34:08Z (8 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
9185e42
Parents:
0d9b4a8 (diff), 73d8600 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge from lp:~jakub/helenos/sun4u

This merge brings support for serial console on the QEMU sun4u machine
and by extension on any system that provides at least one device driver
for a serial port device in the 'serial' location service category and
points the 'console' boot argument to it.

The 'console' boot argument is used to differentiate character devices
that are used as a console from other character devices that may be used
for other purposes (e.g. SLIP or keyboard).

Support for real-world sun4u machines is temporarily broken. The legacy
ns16550 input port driver has been discontinued. Real-world Ultra 5,
which is fairly close to the QEMU machine should be easy to revive. In
order to support the sun4u QEMU machine, a new sun4u platform driver was
added. The isa driver was modified to be usable also for the EBUS bus.

On sparc64 the boot argument is passed in the boot-args boot prom
environment variable. On ia32 and amd64, the boot argument can be set in
grub.cfg as an argument to the multiboot command. The backslashes need
to be properly escaped. Other platforms don't have support for boot
arguments yet.

Because the user input/output subsystem is apparently not ready to drive
the serial console next to the ordinary console or the GUI, the serial
console mode is mutually exclusive with the normal
keyboard/ega/fb/compositor mode.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • uspace/drv/bus/pci/pciintel/pci.c

    r0d9b4a8 rbfa4ffa  
    6363#define NAME "pciintel"
    6464
     65#define CONF_ADDR_ENABLE        (1 << 31)
    6566#define CONF_ADDR(bus, dev, fn, reg) \
    66         ((1 << 31) | (bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
     67        ((bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
    6768
    6869/** Obtain PCI function soft-state from DDF function node */
    … …  
    232233        fibril_mutex_lock(&bus->conf_mutex);
    233234
    234         pio_write_32(bus->conf_addr_reg, host2uint32_t_le(conf_addr));
    235 
    236         /*
    237          * Always read full 32-bits from the PCI conf_data_port register and
    238          * get the desired portion of it afterwards. Some architectures do not
    239          * support shorter PIO reads offset from this register.
    240          */
    241         val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
     235        if (bus->conf_addr_reg) {
     236                pio_write_32(bus->conf_addr_reg,
     237                    host2uint32_t_le(CONF_ADDR_ENABLE | conf_addr));
     238                /*
     239                 * Always read full 32-bits from the PCI conf_data_port
     240                 * register and get the desired portion of it afterwards. Some
     241                 * architectures do not support shorter PIO reads offset from
     242                 * this register.
     243                 */
     244                val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
     245        } else {
     246                val = uint32_t_le2host(pio_read_32(
     247                    &bus->conf_space[conf_addr / sizeof(ioport32_t)]));
     248        }
    242249
    243250        switch (len) {
    … …  
    260267        const uint32_t conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
    261268        pci_bus_t *bus = pci_bus_from_fun(fun);
    262         uint32_t val = 0; // Prevent -Werror=maybe-uninitialized
     269        uint32_t val;
    263270       
    264271        fibril_mutex_lock(&bus->conf_mutex);
    … …  
    275282                 * missing bits first.
    276283                 */
    277                 pio_write_32(bus->conf_addr_reg, host2uint32_t_le(conf_addr));
    278                 val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
     284                if (bus->conf_addr_reg) {
     285                        pio_write_32(bus->conf_addr_reg,
     286                            host2uint32_t_le(CONF_ADDR_ENABLE | conf_addr));
     287                        val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
     288                } else {
     289                        val = uint32_t_le2host(pio_read_32(
     290                            &bus->conf_space[conf_addr / sizeof(ioport32_t)]));
     291                }
    279292        }
    280293       
    … …  
    293306        }
    294307
    295         pio_write_32(bus->conf_addr_reg, host2uint32_t_le(conf_addr));
    296         pio_write_32(bus->conf_data_reg, host2uint32_t_le(val));
     308        if (bus->conf_addr_reg) {
     309                pio_write_32(bus->conf_addr_reg,
     310                    host2uint32_t_le(CONF_ADDR_ENABLE | conf_addr));
     311                pio_write_32(bus->conf_data_reg, host2uint32_t_le(val));
     312        } else {
     313                pio_write_32(&bus->conf_space[conf_addr / sizeof(ioport32_t)],
     314                    host2uint32_t_le(val));
     315        }
    297316       
    298317        fibril_mutex_unlock(&bus->conf_mutex);
    … …  
    620639                        ddf_msg(LVL_DEBUG, "Adding new function %s.",
    621640                            ddf_fun_get_name(fun->fnode));
    622                        
     641
    623642                        pci_fun_create_match_ids(fun);
    624643                       
    … …  
    688707       
    689708       
    690         assert(hw_resources.count > 1);
    691         assert(hw_resources.resources[0].type == IO_RANGE);
    692         assert(hw_resources.resources[0].res.io_range.size >= 4);
    693        
    694         assert(hw_resources.resources[1].type == IO_RANGE);
    695         assert(hw_resources.resources[1].res.io_range.size >= 4);
    696        
    697         ddf_msg(LVL_DEBUG, "conf_addr = %" PRIx64 ".",
    698             hw_resources.resources[0].res.io_range.address);
    699         ddf_msg(LVL_DEBUG, "data_addr = %" PRIx64 ".",
    700             hw_resources.resources[1].res.io_range.address);
    701        
    702         if (pio_enable_resource(&bus->pio_win, &hw_resources.resources[0],
    703             (void **) &bus->conf_addr_reg)) {
    704                 ddf_msg(LVL_ERROR, "Failed to enable configuration ports.");
    705                 rc = EADDRNOTAVAIL;
    706                 goto fail;
    707         }
    708         if (pio_enable_resource(&bus->pio_win, &hw_resources.resources[1],
    709             (void **) &bus->conf_data_reg)) {
    710                 ddf_msg(LVL_ERROR, "Failed to enable configuration ports.");
    711                 rc = EADDRNOTAVAIL;
    712                 goto fail;
     709        assert(hw_resources.count >= 1);
     710
     711        if (hw_resources.count == 1) {
     712                assert(hw_resources.resources[0].type == MEM_RANGE);
     713
     714                ddf_msg(LVL_DEBUG, "conf_addr_space = %" PRIx64 ".",
     715                    hw_resources.resources[0].res.mem_range.address);
     716
     717                if (pio_enable_resource(&bus->pio_win,
     718                    &hw_resources.resources[0],
     719                    (void **) &bus->conf_space)) {
     720                        ddf_msg(LVL_ERROR,
     721                            "Failed to map configuration space.");
     722                        rc = EADDRNOTAVAIL;
     723                        goto fail;
     724                }
     725               
     726        } else {
     727                assert(hw_resources.resources[0].type == IO_RANGE);
     728                assert(hw_resources.resources[0].res.io_range.size >= 4);
     729       
     730                assert(hw_resources.resources[1].type == IO_RANGE);
     731                assert(hw_resources.resources[1].res.io_range.size >= 4);
     732       
     733                ddf_msg(LVL_DEBUG, "conf_addr = %" PRIx64 ".",
     734                    hw_resources.resources[0].res.io_range.address);
     735                ddf_msg(LVL_DEBUG, "data_addr = %" PRIx64 ".",
     736                    hw_resources.resources[1].res.io_range.address);
     737       
     738                if (pio_enable_resource(&bus->pio_win,
     739                    &hw_resources.resources[0],
     740                    (void **) &bus->conf_addr_reg)) {
     741                        ddf_msg(LVL_ERROR,
     742                            "Failed to enable configuration ports.");
     743                        rc = EADDRNOTAVAIL;
     744                        goto fail;
     745                }
     746                if (pio_enable_resource(&bus->pio_win,
     747                    &hw_resources.resources[1],
     748                    (void **) &bus->conf_data_reg)) {
     749                        ddf_msg(LVL_ERROR,
     750                            "Failed to enable configuration ports.");
     751                        rc = EADDRNOTAVAIL;
     752                        goto fail;
     753                }
    713754        }
    714755       
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