Changeset bd48f4c in mainline for kernel/arch/ia32/include/interrupt.h

Timestamp:

2010-07-12T10:53:30Z (15 years ago)

Author:

Jiri Svoboda <jiri@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

bd11d3e

Parents:

c40e6ef (diff), bee2d4c (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge mainline changes.

File:

• kernel/arch/ia32/include/interrupt.h (modified) (2 diffs)

kernel/arch/ia32/include/interrupt.h

@@ -38 +38 @@
 #include <typedefs.h>
 #include <arch/pm.h>
+#include <trace.h>
 
-#define IVT_ITEMS       IDT_ITEMS
-#define IVT_FIRST       0
+#define IVT_ITEMS  IDT_ITEMS
+#define IVT_FIRST  0
 
-#define EXC_COUNT       32
-#define IRQ_COUNT       16
+#define EXC_COUNT  32
+#define IRQ_COUNT  16
 
-#define IVT_EXCBASE     0
-#define IVT_IRQBASE     (IVT_EXCBASE + EXC_COUNT)
-#define IVT_FREEBASE    (IVT_IRQBASE + IRQ_COUNT)
+#define IVT_EXCBASE   0
+#define IVT_IRQBASE   (IVT_EXCBASE + EXC_COUNT)
+#define IVT_FREEBASE  (IVT_IRQBASE + IRQ_COUNT)
 
-#define IRQ_CLK         0
-#define IRQ_KBD         1
-#define IRQ_PIC1        2
-#define IRQ_PIC_SPUR    7
-#define IRQ_MOUSE       12
-#define IRQ_DP8390      9
+#define IRQ_CLK       0
+#define IRQ_KBD       1
+#define IRQ_PIC1      2
+#define IRQ_PIC_SPUR  7
+#define IRQ_MOUSE     12
+#define IRQ_DP8390    9
 
-/* this one must have four least significant bits set to ones */
-#define VECTOR_APIC_SPUR        (IVT_ITEMS - 1)
+/* This one must have four least significant bits set to ones */
+#define VECTOR_APIC_SPUR  (IVT_ITEMS - 1)
 
 #if (((VECTOR_APIC_SPUR + 1) % 16) || VECTOR_APIC_SPUR >= IVT_ITEMS)
@@ -63 +64 @@
 #endif
 
-#define VECTOR_DEBUG                    1
-#define VECTOR_CLK                      (IVT_IRQBASE + IRQ_CLK)
-#define VECTOR_PIC_SPUR                 (IVT_IRQBASE + IRQ_PIC_SPUR)
-#define VECTOR_SYSCALL                  IVT_FREEBASE
-#define VECTOR_TLB_SHOOTDOWN_IPI        (IVT_FREEBASE + 1)
-#define VECTOR_DEBUG_IPI                (IVT_FREEBASE + 2)
+#define VECTOR_DEBUG              1
+#define VECTOR_CLK                (IVT_IRQBASE + IRQ_CLK)
+#define VECTOR_PIC_SPUR           (IVT_IRQBASE + IRQ_PIC_SPUR)
+#define VECTOR_SYSCALL            IVT_FREEBASE
+#define VECTOR_TLB_SHOOTDOWN_IPI  (IVT_FREEBASE + 1)
+#define VECTOR_DEBUG_IPI          (IVT_FREEBASE + 2)
 
 typedef struct istate {
+        /*
+         * The strange order of the GPRs is given by the requirement to use the
+         * istate structure for both regular interrupts and exceptions as well
+         * as for syscall handlers which use this order as an optimization.
+         */
+        uint32_t edx;
+        uint32_t ecx;
+        uint32_t ebx;
+        uint32_t esi;
+        uint32_t edi;
+        uint32_t ebp;
         uint32_t eax;
-        uint32_t ecx;
-        uint32_t edx;
-        uint32_t ebp;
-
+        
+        uint32_t ebp_frame;  /* imitation of frame pointer linkage */
+        uint32_t eip_frame;  /* imitation of return address linkage */
+        
         uint32_t gs;
         uint32_t fs;
         uint32_t es;
         uint32_t ds;
-
-        uint32_t error_word;
+        
+        uint32_t error_word;  /* real or fake error word */
         uint32_t eip;
         uint32_t cs;
         uint32_t eflags;
-        uint32_t stack[];
+        uint32_t esp;         /* only if istate_t is from uspace */
+        uint32_t ss;          /* only if istate_t is from uspace */
 } istate_t;
 
 /** Return true if exception happened while in userspace */
-static inline int istate_from_uspace(istate_t *istate)
+NO_TRACE static inline int istate_from_uspace(istate_t *istate)
 {
         return !(istate->eip & 0x80000000);
 }
 
-static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr)
+NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
+    uintptr_t retaddr)
 {
         istate->eip = retaddr;
 }
 
-static inline unative_t istate_get_pc(istate_t *istate)
+NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)
 {
         return istate->eip;
 }
 
-static inline unative_t istate_get_fp(istate_t *istate)
+NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)
 {
         return istate->ebp;
 }
 
-extern void (* disable_irqs_function)(uint16_t irqmask);
-extern void (* enable_irqs_function)(uint16_t irqmask);
+extern void (* disable_irqs_function)(uint16_t);
+extern void (* enable_irqs_function)(uint16_t);
 extern void (* eoi_function)(void);
 
-extern void decode_istate(istate_t *istate);
 extern void interrupt_init(void);
-extern void trap_virtual_enable_irqs(uint16_t irqmask);
-extern void trap_virtual_disable_irqs(uint16_t irqmask);
+extern void trap_virtual_enable_irqs(uint16_t);
+extern void trap_virtual_disable_irqs(uint16_t);
 
 #endif