Changeset b5e68c8 in mainline for kernel/arch/ia32/src/smp/apic.c

Timestamp:

2011-05-12T16:49:44Z (14 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

f36787d7

Parents:

e80329d6 (diff), 750636a (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge mainline changes.

File:

• kernel/arch/ia32/src/smp/apic.c (modified) (4 diffs)

kernel/arch/ia32/src/smp/apic.c

@@ -72 +72 @@
  *
  */
-volatile uint32_t *l_apic = (uint32_t *) 0xfee00000;
-volatile uint32_t *io_apic = (uint32_t *) 0xfec00000;
+volatile uint32_t *l_apic = (uint32_t *) UINT32_C(0xfee00000);
+volatile uint32_t *io_apic = (uint32_t *) UINT32_C(0xfec00000);
 
 uint32_t apic_id_mask = 0;
@@ -178 +178 @@
         disable_irqs_function = io_apic_disable_irqs;
         eoi_function = l_apic_eoi;
+        irqs_info = "apic";
         
         /*
@@ -184 +185 @@
          * Other interrupts will be forwarded to the lowest priority CPU.
          */
-        io_apic_disable_irqs(0xffff);
+        io_apic_disable_irqs(0xffffU);
         
         irq_initialize(&l_apic_timer_irq);
@@ -477 +478 @@
 {
 #ifdef LAPIC_VERBOSE
-        printf("LVT on cpu%" PRIs ", LAPIC ID: %" PRIu8 "\n",
+        printf("LVT on cpu%u, LAPIC ID: %" PRIu8 "\n",
             CPU->id, l_apic_id());