Changeset b473611 in mainline for kernel/arch/sparc64/include/trap/mmu.h

Timestamp:

2010-02-13T23:56:33Z (15 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

e3a3a619

Parents:

e70edd1 (diff), b86d436 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge the sparc branch.
Both sun4u and sun4v appear to work.
HM cleanup is pending.

File:

• kernel/arch/sparc64/include/trap/mmu.h (modified) (1 diff)

kernel/arch/sparc64/include/trap/mmu.h

@@ -38 +38 @@
 #define KERN_sparc64_MMU_TRAP_H_
 
-#include <arch/stack.h>
-#include <arch/regdef.h>
-#include <arch/mm/tlb.h>
-#include <arch/mm/mmu.h>
-#include <arch/mm/tte.h>
-#include <arch/trap/regwin.h>
-
-#ifdef CONFIG_TSB
-#include <arch/mm/tsb.h>
+#if defined (SUN4U)
+#include <arch/trap/sun4u/mmu.h>
+#elif defined (SUN4V)
+#include <arch/trap/sun4v/mmu.h>
 #endif
-
-#define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS     0x64
-#define TT_FAST_DATA_ACCESS_MMU_MISS            0x68
-#define TT_FAST_DATA_ACCESS_PROTECTION          0x6c
-
-#define FAST_MMU_HANDLER_SIZE                   128
-
-#ifdef __ASM__
-
-.macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
-        /*
-         * First, try to refill TLB from TSB.
-         */
-#ifdef CONFIG_TSB
-        ldxa [%g0] ASI_IMMU, %g1                        ! read TSB Tag Target Register
-        ldxa [%g0] ASI_IMMU_TSB_8KB_PTR_REG, %g2        ! read TSB 8K Pointer
-        ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4            ! 16-byte atomic load into %g4 and %g5
-        cmp %g1, %g4                                    ! is this the entry we are looking for?
-        bne,pn %xcc, 0f
-        nop
-        stxa %g5, [%g0] ASI_ITLB_DATA_IN_REG            ! copy mapping from ITSB to ITLB
-        retry
-#endif
-
-0:
-        wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
-        PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss
-.endm
-
-.macro FAST_DATA_ACCESS_MMU_MISS_HANDLER tl
-        /*
-         * First, try to refill TLB from TSB.
-         */
-
-#ifdef CONFIG_TSB
-        ldxa [%g0] ASI_DMMU, %g1                        ! read TSB Tag Target Register
-        srlx %g1, TSB_TAG_TARGET_CONTEXT_SHIFT, %g2     ! is this a kernel miss?
-        brz,pn %g2, 0f
-        ldxa [%g0] ASI_DMMU_TSB_8KB_PTR_REG, %g3        ! read TSB 8K Pointer
-        ldda [%g3] ASI_NUCLEUS_QUAD_LDD, %g4            ! 16-byte atomic load into %g4 and %g5
-        cmp %g1, %g4                                    ! is this the entry we are looking for?
-        bne,pn %xcc, 0f
-        nop
-        stxa %g5, [%g0] ASI_DTLB_DATA_IN_REG            ! copy mapping from DTSB to DTLB
-        retry
-#endif
-
-        /*
-         * Second, test if it is the portion of the kernel address space
-         * which is faulting. If that is the case, immediately create
-         * identity mapping for that page in DTLB. VPN 0 is excluded from
-         * this treatment.
-         *
-         * Note that branch-delay slots are used in order to save space.
-         */
-0:
-        sethi %hi(fast_data_access_mmu_miss_data_hi), %g7
-        wr %g0, ASI_DMMU, %asi
-        ldxa [VA_DMMU_TAG_ACCESS] %asi, %g1             ! read the faulting Context and VPN
-        set TLB_TAG_ACCESS_CONTEXT_MASK, %g2
-        andcc %g1, %g2, %g3                             ! get Context
-        bnz %xcc, 0f                                    ! Context is non-zero
-        andncc %g1, %g2, %g3                            ! get page address into %g3
-        bz  %xcc, 0f                                    ! page address is zero
-        ldx [%g7 + %lo(end_of_identity)], %g4
-        cmp %g3, %g4
-        bgeu %xcc, 0f
-
-        ldx [%g7 + %lo(kernel_8k_tlb_data_template)], %g2
-        add %g3, %g2, %g2
-        stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG            ! identity map the kernel page
-        retry
-
-        /*
-         * Third, catch and handle special cases when the trap is caused by
-         * the userspace register window spill or fill handler. In case
-         * one of these two traps caused this trap, we just lower the trap
-         * level and service the DTLB miss. In the end, we restart
-         * the offending SAVE or RESTORE.
-         */
-0:
-.if (\tl > 0)
-        wrpr %g0, 1, %tl
-.endif
-
-        /*
-         * Switch from the MM globals.
-         */
-        wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
-
-        /*
-         * Read the Tag Access register for the higher-level handler.
-         * This is necessary to survive nested DTLB misses.
-         */     
-        ldxa [VA_DMMU_TAG_ACCESS] %asi, %g2
-
-        /*
-         * g2 will be passed as an argument to fast_data_access_mmu_miss().
-         */
-        PREEMPTIBLE_HANDLER fast_data_access_mmu_miss
-.endm
-
-.macro FAST_DATA_ACCESS_PROTECTION_HANDLER tl
-        /*
-         * The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER.
-         */
-
-.if (\tl > 0)
-        wrpr %g0, 1, %tl
-.endif
-
-        /*
-         * Switch from the MM globals.
-         */
-        wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
-
-        /*
-         * Read the Tag Access register for the higher-level handler.
-         * This is necessary to survive nested DTLB misses.
-         */     
-        mov VA_DMMU_TAG_ACCESS, %g2
-        ldxa [%g2] ASI_DMMU, %g2
-
-        /*
-         * g2 will be passed as an argument to fast_data_access_mmu_miss().
-         */
-        PREEMPTIBLE_HANDLER fast_data_access_protection
-.endm
-
-#endif /* __ASM__ */
 
 #endif