Changeset ae7d03c in mainline for uspace/drv/bus/pci/pciintel/pci.c

Timestamp:

2018-05-10T13:39:19Z (7 years ago)

Author:

Jiri Svoboda <jiri@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

e8975278

Parents:

b277bef

git-author:

Jiri Svoboda <jiri@…> (2018-05-10 07:38:12)

git-committer:

Jiri Svoboda <jiri@…> (2018-05-10 13:39:19)

Message:

Selected ccheck-proposed comment fixes.

File:

• uspace/drv/bus/pci/pciintel/pci.c (modified) (3 diffs)

uspace/drv/bus/pci/pciintel/pci.c

@@ -267 +267 @@
                  * architectures do not support shorter PIO reads offset from
                  * this register.
-                 */
+                 */
                 val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
         } else {
@@ -301 +301 @@
          * Some architectures do not support shorter PIO writes offset from this
          * register.
-         */
+         */
 
         if (len < 4) {
                 /*
-                 * We have fewer than full 32-bits, so we need to read the
-                 * missing bits first.
-                 */
+                 * We have fewer than full 32-bits, so we need to read the
+                 * missing bits first.
+                 */
                 if (bus->conf_addr_reg) {
                         pio_write_32(bus->conf_addr_reg,
@@ -534 +534 @@
 
         /*
-         * Unimplemented BARs read back as all 0's.
-         */
+         * Unimplemented BARs read back as all 0's.
+         */
         if (!bar)
                 return addr + (addrw64 ? 8 : 4);