Changeset ae7d03c in mainline for uspace/drv/block/ahci/ahci_hw.h
- Timestamp:
- 2018-05-10T13:39:19Z (7 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- e8975278
- Parents:
- b277bef
- git-author:
- Jiri Svoboda <jiri@…> (2018-05-10 07:38:12)
- git-committer:
- Jiri Svoboda <jiri@…> (2018-05-10 13:39:19)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/block/ahci/ahci_hw.h
rb277bef rae7d03c 216 216 typedef union { 217 217 struct { 218 /** Indicates the completion status of BIST219 * non-zero value indicates a failure.220 */221 unsigned int cc : 4;222 /** Reserved. */223 unsigned int reserved : 2;224 /** Software sets this bit to 1 to invoke BIST,225 * the HBA clears this bit to 0 when BIST is complete.226 */227 unsigned int sb : 1;228 /** BIST capable. */229 unsigned int bc : 1;218 /** Indicates the completion status of BIST 219 * non-zero value indicates a failure. 220 */ 221 unsigned int cc : 4; 222 /** Reserved. */ 223 unsigned int reserved : 2; 224 /** Software sets this bit to 1 to invoke BIST, 225 * the HBA clears this bit to 0 when BIST is complete. 226 */ 227 unsigned int sb : 1; 228 /** BIST capable. */ 229 unsigned int bc : 1; 230 230 }; 231 231 uint8_t u8; … … 252 252 253 253 /** AHCI PCI register Subsystem Identifiers. */ 254 typedef struct 255 { 254 typedef struct { 256 255 /** Sub system vendor identifier. */ 257 256 uint8_t ssvid; … … 261 260 262 261 /** AHCI PCI registers Expansion ROM Base Address. */ 263 typedef struct 264 { 262 typedef struct { 265 263 /** Indicates the base address of the HBA expansion ROM. */ 266 264 uint32_t u32; … … 268 266 269 267 /** AHCI PCI register Capabilities Pointer. */ 270 typedef struct 271 { 268 typedef struct { 272 269 /** Indicates the first capability pointer offset. */ 273 270 uint8_t u8; … … 275 272 276 273 /** AHCI PCI register Interrupt Information. */ 277 typedef struct 278 { 274 typedef struct { 279 275 /* Software written value to indicate which interrupt vector 280 276 * the interrupt is connected to. … … 286 282 287 283 /** AHCI PCI register Min Grant (Optional). */ 288 typedef struct 289 { 284 typedef struct { 290 285 /** Indicates the minimum grant time that the device 291 286 * wishes grant asserted. … … 295 290 296 291 /** AHCI PCI register Max Latency (Optional). */ 297 typedef struct 298 { 292 typedef struct { 299 293 /** Indicates the maximum latency that the device can withstand. */ 300 294 uint8_t u8; … … 431 425 432 426 /** AHCI Memory register Command completion coalescing ports. */ 433 typedef struct 434 { 427 typedef struct { 435 428 /** If a bit is set to 1, the corresponding port is 436 429 * part of the command completion coalescing feature. … … 440 433 441 434 /** AHCI Memory register Enclosure management location. */ 442 typedef struct 443 { 435 typedef struct { 444 436 /** Size of the transmit message buffer area in dwords. */ 445 437 uint16_t sz; … … 525 517 526 518 /** AHCI Memory register Generic Host Control. */ 527 typedef struct 528 { 519 typedef struct { 529 520 /** Host Capabilities */ 530 521 uint32_t cap; … … 942 933 943 934 /** AHCI Memory register Port. */ 944 typedef volatile struct 945 { 935 typedef volatile struct { 946 936 /** Port x Command List Base Address. */ 947 937 uint32_t pxclb; … … 1010 1000 /** Physical Region Descriptor Byte Count. */ 1011 1001 uint32_t bytesprocessed; 1012 1002 /** Command Table Descriptor Base Address. */ 1013 1003 uint32_t cmdtable; 1014 1004 /** Command Table Descriptor Base Address Upper 32-bits. */
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