Changeset ae7d03c in mainline for kernel/arch/arm32/src/cpu/cpu.c

Timestamp:

2018-05-10T13:39:19Z (7 years ago)

Author:

Jiri Svoboda <jiri@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

e8975278

Parents:

b277bef

git-author:

Jiri Svoboda <jiri@…> (2018-05-10 07:38:12)

git-committer:

Jiri Svoboda <jiri@…> (2018-05-10 13:39:19)

Message:

Selected ccheck-proposed comment fixes.

File:

• kernel/arch/arm32/src/cpu/cpu.c (modified) (1 diff)

kernel/arch/arm32/src/cpu/cpu.c

@@ -169 +169 @@
 #endif
 #ifdef PROCESSOR_ARCH_armv7_a
-         /* ICache coherency is elaborated on in barrier.h.
-          * VIPT and PIPT caches need maintenance only on code modify,
-          * so it should be safe for general use.
-          * Enable branch predictors too as they follow the same rules
-          * as ICache and they can be flushed together
-          */
+        /* ICache coherency is elaborated on in barrier.h.
+         * VIPT and PIPT caches need maintenance only on code modify,
+         * so it should be safe for general use.
+         * Enable branch predictors too as they follow the same rules
+         * as ICache and they can be flushed together
+         */
         if ((CTR_read() & CTR_L1I_POLICY_MASK) != CTR_L1I_POLICY_AIVIVT) {
                 control_reg |=