Changeset a7961271 in mainline for kernel/arch/sparc64/include/trap/mmu.h

Timestamp:

2006-08-26T18:42:11Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

c8ea4a8b

Parents:

f47fd19

Message:

sparc64 work.
Bunch of changes in preparation for sparc64 mm and userspace support.
Fix alignment of hardcoded_* variables in linker script.

File:

• kernel/arch/sparc64/include/trap/mmu.h (modified) (5 diffs)

kernel/arch/sparc64/include/trap/mmu.h

@@ -39 +39 @@
 
 #include <arch/stack.h>
+#include <arch/regdef.h>
 #include <arch/mm/tlb.h>
 #include <arch/mm/mmu.h>
@@ -60 +61 @@
 .macro FAST_DATA_ACCESS_MMU_MISS_HANDLER
         /*
-         * First, test if it is the portion of the kernel address space
+         * First, try to refill TLB from TSB.
+         */
+        ! TODO
+
+        /*
+         * Second, test if it is the portion of the kernel address space
          * which is faulting. If that is the case, immediately create
          * identity mapping for that page in DTLB. VPN 0 is excluded from
@@ -67 +73 @@
          * Note that branch-delay slots are used in order to save space.
          */
+0:
         mov VA_DMMU_TAG_ACCESS, %g1
         ldxa [%g1] ASI_DMMU, %g1                        ! read the faulting Context and VPN
@@ -75 +82 @@
         bz 0f                                           ! page address is zero
 
-        /*
-         * Create and insert the identity-mapped entry for
-         * the faulting kernel page.
-         */
-        
         or %g3, (TTE_CP|TTE_P|TTE_W), %g2               ! 8K pages are the default (encoded as 0)
         set 1, %g3
@@ -87 +89 @@
         retry
 
+        /*
+         * Third, catch and handle special cases when the trap is caused by
+         * some register window trap handler.
+         */
 0:
-        save %sp, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp                                             
+        ! TODO
+
+0:
+        wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
         PREEMPTIBLE_HANDLER fast_data_access_mmu_miss
 .endm