Changeset a35b458 in mainline for kernel/arch/sparc64/src/trap/sun4u
- Timestamp:
- 2018-03-02T20:10:49Z (8 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- f1380b7
- Parents:
- 3061bc1
- git-author:
- Jiří Zárevúcky <zarevucky.jiri@…> (2018-02-28 17:38:31)
- git-committer:
- Jiří Zárevúcky <zarevucky.jiri@…> (2018-03-02 20:10:49)
- Location:
- kernel/arch/sparc64/src/trap/sun4u
- Files:
-
- 2 edited
-
interrupt.c (modified) (5 diffs)
-
trap_table.S (modified) (7 diffs)
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/sparc64/src/trap/sun4u/interrupt.c
r3061bc1 ra35b458 58 58 if (status & (!INTR_DISPATCH_STATUS_BUSY)) 59 59 panic("Interrupt Dispatch Status busy bit not set\n"); 60 60 61 61 uint64_t intrcv = asi_u64_read(ASI_INTR_RECEIVE, 0); 62 62 #if defined (US) … … 65 65 uint64_t data0 = asi_u64_read(ASI_INTR_R, VA_INTR_R_DATA_0); 66 66 #endif 67 67 68 68 irq_t *irq = irq_dispatch_and_lock(data0); 69 69 if (irq) { … … 72 72 */ 73 73 irq->handler(irq); 74 74 75 75 /* 76 76 * See if there is a clear-interrupt-routine and call it. … … 78 78 if (irq->cir) 79 79 irq->cir(irq->cir_arg, irq->inr); 80 80 81 81 irq_spinlock_unlock(&irq->lock, false); 82 82 } else if (data0 > config.base) { … … 103 103 #endif 104 104 } 105 105 106 106 membar(); 107 107 asi_u64_write(ASI_INTR_RECEIVE, 0, 0); -
kernel/arch/sparc64/src/trap/sun4u/trap_table.S
r3061bc1 ra35b458 502 502 .if NOT(\is_syscall) 503 503 rdpr %tstate, %g3 504 504 505 505 /* 506 506 * One of the ways this handler can be invoked is after a nested MMU trap from … … 576 576 */ 577 577 wrpr %g0, WSTATE_OTHER(0) | WSTATE_NORMAL(0), %wstate 578 578 579 579 /* 580 580 * Copy arguments. … … 605 605 */ 606 606 stx %g4, [%sp + STACK_BIAS + ISTATE_OFFSET_Y] 607 607 608 608 wrpr %g0, 0, %tl 609 609 wrpr %g0, PSTATE_PRIV_BIT | PSTATE_PEF_BIT, %pstate 610 610 SAVE_GLOBALS 611 611 612 612 .if NOT(\is_syscall) 613 613 /* … … 629 629 wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate 630 630 wrpr %g0, 1, %tl 631 631 632 632 /* 633 633 * Read TSTATE, TPC and TNPC from saved copy. … … 742 742 rd %pc, %g1 743 743 flush %g1 744 744 745 745 rdpr %cwp, %g1 746 746 rdpr %otherwin, %g2 … … 800 800 mov NWINDOWS - 2, %g1 ! use dealy slot for both cases 801 801 sub %g1, %g2, %g1 802 802 803 803 wrpr %g0, 0, %otherwin 804 804 wrpr %g1, 0, %cansave ! NWINDOWS - 2 - CANRESTORE … … 845 845 and %g1, NWINDOWS - 1, %g1 846 846 wrpr %g1, 0, %cwp ! CWP-- 847 847 848 848 .if \is_syscall 849 849 done
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