Changeset 1b20da0 in mainline for kernel/arch/sparc64/src/trap/sun4u

Timestamp:

2018-02-28T17:52:03Z (8 years ago)

Author:

Jiří Zárevúcky <zarevucky.jiri@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

3061bc1

Parents:

df6ded8

git-author:

Jiří Zárevúcky <zarevucky.jiri@…> (2018-02-28 17:26:03)

git-committer:

Jiří Zárevúcky <zarevucky.jiri@…> (2018-02-28 17:52:03)

Message:

style: Remove trailing whitespace on non-empty lines, in certain file types.

Command used: tools/srepl '\([^[:space:]]\)\s\+$' '\1' -- *.c *.h *.py *.sh *.s *.S *.ag

File:

• kernel/arch/sparc64/src/trap/sun4u/trap_table.S (modified) (12 diffs)

kernel/arch/sparc64/src/trap/sun4u/trap_table.S

@@ -64 +64 @@
         mov TT_INSTRUCTION_ACCESS_EXCEPTION, %g2
         clr %g5
-        PREEMPTIBLE_HANDLER exc_dispatch 
+        PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x0a, TL = 0, instruction_access_error */
@@ -71 +71 @@
         mov TT_INSTRUCTION_ACCESS_ERROR, %g2
         clr %g5
-        PREEMPTIBLE_HANDLER exc_dispatch 
+        PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x10, TL = 0, illegal_instruction */
@@ -78 +78 @@
         mov TT_ILLEGAL_INSTRUCTION, %g2
         clr %g5
-        PREEMPTIBLE_HANDLER exc_dispatch 
+        PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x11, TL = 0, privileged_opcode */
@@ -85 +85 @@
         mov TT_PRIVILEGED_OPCODE, %g2
         clr %g5
-        PREEMPTIBLE_HANDLER exc_dispatch 
+        PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x12, TL = 0, unimplemented_LDD */
@@ -92 +92 @@
         mov TT_UNIMPLEMENTED_LDD, %g2
         clr %g5
-        PREEMPTIBLE_HANDLER exc_dispatch 
+        PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x13, TL = 0, unimplemented_STD */
@@ -106 +106 @@
         mov TT_FP_DISABLED, %g2
         clr %g5
-        PREEMPTIBLE_HANDLER exc_dispatch 
+        PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x21, TL = 0, fb_exception_ieee_754 handler */
@@ -168 +168 @@
         mov TT_LDDF_MEM_ADDRESS_NOT_ALIGNED, %g2
         clr %g5
-        PREEMPTIBLE_HANDLER exc_dispatch 
+        PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x36, TL = 0, STDF_mem_address_not_aligned */
@@ -382 +382 @@
         mov TT_INSTRUCTION_ACCESS_EXCEPTION, %g2
         clr %g5
-        PREEMPTIBLE_HANDLER exc_dispatch 
+        PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x0a, TL > 0, instruction_access_error */
@@ -489 +489 @@
  * TL1: preemptible trap handler started after a tick interrupt
  * TL2: preemptible trap handler did SAVE
- * TL3: spill handler touched the kernel stack  
+ * TL3: spill handler touched the kernel stack
  * TL4: hardware or software failure
  *
@@ -510 +510 @@
          * trap is resolved. However, because we are in the wrong window from the
          * perspective of the MMU trap, we need to synchronize CWP with CWP from TL=0.
-         */ 
+         */
         and %g3, TSTATE_CWP_MASK, %g4
         wrpr %g4, 0, %cwp                       ! resynchronize CWP
@@ -566 +566 @@
 
         /*
-         * At this moment, we are using the kernel stack 
+         * At this moment, we are using the kernel stack
          * and have successfully allocated a register window.
          */
@@ -585 +585 @@
 .else
         ! store the syscall number on the stack as 7th argument
-        stx %g2, [%sp + STACK_BIAS + ISTATE_OFFSET_ARG6] 
+        stx %g2, [%sp + STACK_BIAS + ISTATE_OFFSET_ARG6]
 .endif