Changeset a35b458 in mainline for kernel/arch/sparc64/src/sun4u/start.S
- Timestamp:
- 2018-03-02T20:10:49Z (7 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- f1380b7
- Parents:
- 3061bc1
- git-author:
- Jiří Zárevúcky <zarevucky.jiri@…> (2018-02-28 17:38:31)
- git-committer:
- Jiří Zárevúcky <zarevucky.jiri@…> (2018-03-02 20:10:49)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/sparc64/src/sun4u/start.S
r3061bc1 ra35b458 85 85 ! Get bits (PHYSMEM_ADDR_SIZE - 1):13 of physmem_base. 86 86 srlx %l6, 13, %l5 87 87 88 88 ! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13] 89 89 sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5 … … 101 101 wrpr %g0, NWINDOWS - 1, %cleanwin ! prevent needless clean_window 102 102 ! traps for kernel 103 103 104 104 wrpr %g0, 0, %wstate ! use default spill/fill trap 105 105 … … 132 132 set (TLB_DEMAP_CONTEXT << TLB_DEMAP_TYPE_SHIFT) | (context_id << \ 133 133 TLB_DEMAP_CONTEXT_SHIFT), %r1 134 134 135 135 ! demap context 0 136 136 SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS) … … 161 161 sllx %r2, TTE_V_SHIFT, %r2; \ 162 162 or %r1, %r2, %r1; 163 163 164 164 ! write DTLB data and install the kernel mapping 165 165 SET_TLB_DATA(g1, g2, TTE_L | TTE_W) ! use non-global mapping … … 182 182 stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG 183 183 membar #Sync 184 184 185 185 /* 186 186 * Now is time to take over the IMMU. Unfortunatelly, it cannot be done … … 202 202 * the taken over DTLB. 203 203 */ 204 204 205 205 set kernel_image_start, %g5 206 206 207 207 ! write ITLB tag of context 1 208 208 SET_TLB_TAG(g1, MEM_CONTEXT_TEMP) … … 215 215 stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG 216 216 flush %g5 217 217 218 218 ! switch to context 1 219 219 mov MEM_CONTEXT_TEMP, %g1 220 220 stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! 221 221 flush %g5 222 222 223 223 ! demap context 0 224 224 SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS) 225 225 stxa %g0, [%g1] ASI_IMMU_DEMAP 226 226 flush %g5 227 227 228 228 ! write ITLB tag of context 0 229 229 SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL) … … 244 244 stxa %g0, [%g1] ASI_IMMU_DEMAP 245 245 flush %g5 246 246 247 247 ! set context 0 in the primary context register 248 248 stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! 249 249 flush %g5 250 250 251 251 ! leave nucleus - using primary context, i.e. context 0 252 252 wrpr %g0, 0, %tl … … 271 271 or %l3, %l5, %l3 272 272 stx %l3, [%l4 + %lo(kernel_8k_tlb_data_template)] 273 273 274 274 ! flush the whole D-cache 275 275 set (DCACHE_SIZE - DCACHE_LINE_SIZE), %g1 276 276 stxa %g0, [%g1] ASI_DCACHE_TAG 277 277 278 278 0: 279 279 membar #Sync … … 282 282 stxa %g0, [%g1] ASI_DCACHE_TAG 283 283 membar #Sync 284 284 285 285 /* 286 286 * So far, we have not touched the stack. … … 290 290 or %sp, %lo(temporary_boot_stack), %sp 291 291 sub %sp, STACK_BIAS, %sp 292 292 293 293 /* 294 294 * Call sparc64_pre_main(bootinfo) … … 296 296 call sparc64_pre_main 297 297 mov %o1, %o0 298 298 299 299 /* 300 300 * Create the first stack frame. … … 372 372 /* Not reached. */ 373 373 #endif 374 374 375 375 0: 376 376 ba,a %xcc, 0b
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