Changeset a35b458 in mainline for kernel/arch/sparc64/src/mm/sun4u/tsb.c
- Timestamp:
- 2018-03-02T20:10:49Z (7 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- f1380b7
- Parents:
- 3061bc1
- git-author:
- Jiří Zárevúcky <zarevucky.jiri@…> (2018-02-28 17:38:31)
- git-committer:
- Jiří Zárevúcky <zarevucky.jiri@…> (2018-03-02 20:10:49)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/sparc64/src/mm/sun4u/tsb.c
r3061bc1 ra35b458 57 57 size_t i; 58 58 size_t cnt; 59 59 60 60 assert(as->arch.itsb); 61 61 assert(as->arch.dtsb); 62 62 63 63 i0 = (page >> MMU_PAGE_WIDTH) & ITSB_ENTRY_MASK; 64 64 … … 67 67 else 68 68 cnt = pages * 2; 69 69 70 70 for (i = 0; i < cnt; i++) { 71 71 as->arch.itsb[(i0 + i) & ITSB_ENTRY_MASK].tag.invalid = true; … … 86 86 87 87 assert(index <= 1); 88 88 89 89 as = t->as; 90 90 entry = ((t->page >> MMU_PAGE_WIDTH) + index) & ITSB_ENTRY_MASK; … … 112 112 tte->data.p = t->k; /* p as privileged, k as kernel */ 113 113 tte->data.v = t->p; /* v as valid, p as present */ 114 114 115 115 write_barrier(); 116 116 117 117 tte->tag.invalid = false; /* mark the entry as valid */ 118 118 } … … 129 129 tsb_entry_t *tte; 130 130 size_t entry; 131 131 132 132 assert(index <= 1); 133 133 … … 161 161 tte->data.w = ro ? false : t->w; 162 162 tte->data.v = t->p; 163 163 164 164 write_barrier(); 165 165 166 166 tte->tag.invalid = false; /* mark the entry as valid */ 167 167 }
Note:
See TracChangeset
for help on using the changeset viewer.