Changeset a0d74fd in mainline for arch/ia64/src/mm/tlb.c

Timestamp:

2006-03-01T11:07:04Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

9ad03fe

Parents:

2c49fbbe

Message:

ia64 work.
Provide PA2KA(identity) mapping for kernel data references via Alternate Data TLB Fault handler.
Add before_thread_runs_arch() that maps kstack, if necessary.
Add easy to use dtlb_mapping_insert() for comfortable insertion of kernel data mappings.

File:

• arch/ia64/src/mm/tlb.c (modified) (8 diffs)

arch/ia64/src/mm/tlb.c

@@ -32 +32 @@
 
 #include <mm/tlb.h>
+#include <mm/asid.h>
 #include <arch/mm/tlb.h>
+#include <arch/mm/page.h>
 #include <arch/barrier.h>
 #include <arch/interrupt.h>
 #include <typedefs.h>
 #include <panic.h>
+#include <print.h>
 
 /** Invalidate all TLB entries. */
@@ -85 +88 @@
         bool restore_rr = false;
 
-        if (!(entry.not_present.p))
+        if (!(entry.p))
                 return;
 
-        rr.word = rr_read(VA_REGION(va));
-        if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA_REGION(va))))) {
+        rr.word = rr_read(VA2VRN(va));
+        if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) {
                 /*
                  * The selected region register does not contain required RID.
@@ -97 +100 @@
 
                 rr0 = rr;
-                rr0.map.rid = ASID2RID(asid, VA_REGION(va));
-                rr_write(VA_REGION(va), rr0.word);
+                rr0.map.rid = ASID2RID(asid, VA2VRN(va));
+                rr_write(VA2VRN(va), rr0.word);
                 srlz_d();
                 srlz_i();
@@ -121 +124 @@
         
         if (restore_rr) {
-                rr_write(VA_REGION(va),rr.word);
+                rr_write(VA2VRN(va), rr.word);
                 srlz_d();
                 srlz_i();
@@ -164 +167 @@
         bool restore_rr = false;
 
-        if (!(entry.not_present.p))
+        if (!(entry.p))
                 return;
 
-        rr.word = rr_read(VA_REGION(va));
-        if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA_REGION(va))))) {
+        rr.word = rr_read(VA2VRN(va));
+        if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) {
                 /*
                  * The selected region register does not contain required RID.
@@ -176 +179 @@
 
                 rr0 = rr;
-                rr0.map.rid = ASID2RID(asid, VA_REGION(va));
-                rr_write(VA_REGION(va), rr0.word);
+                rr0.map.rid = ASID2RID(asid, VA2VRN(va));
+                rr_write(VA2VRN(va), rr0.word);
                 srlz_d();
                 srlz_i();
@@ -200 +203 @@
         
         if (restore_rr) {
-                rr_write(VA_REGION(va),rr.word);
-                srlz_d();
-                srlz_i();
-        }
+                rr_write(VA2VRN(va), rr.word);
+                srlz_d();
+                srlz_i();
+        }
+}
+
+/** Insert data into DTLB.
+ *
+ * @param va Virtual page address.
+ * @param asid Address space identifier.
+ * @param entry The rest of TLB entry as required by TLB insertion format.
+ * @param dtr If true, insert into data translation register, use data translation cache otherwise.
+ * @param tr Translation register if dtr is true, ignored otherwise.
+ */
+void dtlb_mapping_insert(__address page, __address frame, bool dtr, index_t tr)
+{
+        tlb_entry_t entry;
+        
+        entry.word[0] = 0;
+        entry.word[1] = 0;
+        
+        entry.p = true;                 /* present */
+        entry.ma = MA_WRITEBACK;
+        entry.a = true;                 /* already accessed */
+        entry.d = true;                 /* already dirty */
+        entry.pl = PL_KERNEL;
+        entry.ar = AR_READ | AR_WRITE;
+        entry.ppn = frame >> PPN_SHIFT;
+        entry.ps = PAGE_WIDTH;
+        
+        if (dtr)
+                dtr_mapping_insert(page, ASID_KERNEL, entry, tr);
+        else
+                dtc_mapping_insert(page, ASID_KERNEL, entry);
 }
 
@@ -211 +244 @@
 }
 
+/** Data TLB fault with VHPT turned off.
+ *
+ * @param vector Interruption vector.
+ * @param pstate Structure with saved interruption state.
+ */
 void alternate_data_tlb_fault(__u64 vector, struct exception_regdump *pstate)
 {
-        panic("%s: %P\n", __FUNCTION__, pstate->cr_ifa);
+        region_register rr;
+        rid_t rid;
+        __address va;
+        
+        va = pstate->cr_ifa;    /* faulting address */
+        rr.word = rr_read(VA2VRN(va));
+        rid = rr.map.rid;
+        if (RID2ASID(rid) == ASID_KERNEL) {
+                if (VA2VRN(va) == VRN_KERNEL) {
+                        /*
+                         * Provide KA2PA(identity) mapping for faulting piece of
+                         * kernel address space.
+                         */
+                        dtlb_mapping_insert(va, KA2PA(va), false, 0);
+                        return;
+                }
+        }
+        panic("%s: va=%P, rid=%d\n", __FUNCTION__, pstate->cr_ifa, rr.map.rid);
 }