Changeset 9ea8a7ca in mainline for arch/sparc64/include/barrier.h


Ignore:
Timestamp:
2006-02-02T12:47:40Z (19 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
758e065
Parents:
4e147a6
Message:

mips32 is not supposed to allocate page table.
This is done by the generic code now.
Remove PTL0 pointer as it is not needed.

Remove GET_PTL0_ADDRESS from kernel.

Update sparc64 comments in barrier.h.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • arch/sparc64/include/barrier.h

    r4e147a6 r9ea8a7ca  
    4040#define write_barrier()
    4141
    42 /** Flush Instruction Memory. */
     42/** Flush Instruction Memory instruction. */
    4343static inline void flush(void)
    4444{
    4545        /*
    46          * The FLUSH instruction takes address parameter,
    47          * but JPS1 implementations are free to ignore it.
    48          * The only requirement is that it is a valid address
    49          * as it is passed to D-MMU.
     46         * The FLUSH instruction takes address parameter.
     47         * As such, it may trap if the address is not found in DTLB.
     48         * However, JPS1 implementations are free to ignore the trap.
    5049         */
    51         __asm__ volatile ("flush %sp\n");       /* %sp is guaranteed to reference mapped memory */
     50        __asm__ volatile ("flush %sp\n");
    5251}
    5352
     53/** Memory Barrier instruction. */
    5454static inline void membar(void)
    5555{
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