Changeset 9ad03fe in mainline for arch/ia64/src/mm/page.c

Timestamp:

2006-03-01T12:58:13Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

03427d0

Parents:

a0d74fd

Message:

ia64 work.
More capable TLB miss handlers.
The ia64 kernel now passes mm/mapping1 test.

Fix generic hash table to properly initialize lists.

Change page_ht() to properly initialize inserted PTE's.
Change format of generic page hash table PTE's.

File:

• arch/ia64/src/mm/page.c (modified) (2 diffs)

arch/ia64/src/mm/page.c

@@ -73 +73 @@
 
         /*
-         * And invalidate the rest of region register.
+         * And setup the rest of region register.
          */
         for(i = 0; i < REGION_REGISTERS; i++) {
@@ -82 +82 @@
                 rr.word == rr_read(i);
                 rr.map.ve = 0;          /* disable VHPT walker */
-                rr.map.rid = RID_INVALID;
+                rr.map.rid = RID_KERNEL;
+                rr.map.ps = PAGE_WIDTH;
                 rr_write(i, rr.word);
                 srlz_i();