Changeset 97f1691 in mainline for arch/sparc64/src/mm/tlb.c


Ignore:
Timestamp:
2006-02-28T00:02:39Z (19 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
7d6ec87
Parents:
d87c3f3
Message:

sparc64 work.
Fix KBD_VIRT_ADDRESS.
Call before_thread_runs() prior to the switch to the thread's stack. Add comment why this is crucial.
Add after_thread_ran() to the scheduler.
Add before_thread_runs_arch() and after_thread_ran_arch() for sparc64, mapping/demapping thread's kernel stack.
Add dummy after_thread_ran_arch() to all other architectures.
Add dtlb_insert_mapping() to promote code reuse.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • arch/sparc64/src/mm/tlb.c

    rd87c3f3 r97f1691  
    110110        dmmu_enable();
    111111        immu_enable();
    112        
    113         /*
    114          * Quick hack: map frame buffer
    115          */
    116         fr.address = FB_PHYS_ADDRESS;
    117         pg.address = FB_VIRT_ADDRESS;
     112}
     113
     114/** Insert privileged mapping into DMMU TLB.
     115 *
     116 * @param page Virtual page address.
     117 * @param frame Physical frame address.
     118 * @param pagesize Page size.
     119 * @param locked True for permanent mappings, false otherwise.
     120 * @param cacheable True if the mapping is cacheable, false otherwise.
     121 */
     122void dtlb_insert_mapping(__address page, __address frame, int pagesize, bool locked, bool cacheable)
     123{
     124        tlb_tag_access_reg_t tag;
     125        tlb_data_t data;
     126        page_address_t pg;
     127        frame_address_t fr;
     128
     129        pg.address = page;
     130        fr.address = frame;
    118131
    119132        tag.value = ASID_KERNEL;
     
    124137        data.value = 0;
    125138        data.v = true;
    126         data.size = PAGESIZE_4M;
     139        data.size = pagesize;
    127140        data.pfn = fr.pfn;
    128         data.l = true;
    129         data.cp = 0;
    130         data.cv = 0;
     141        data.l = locked;
     142        data.cp = cacheable;
     143        data.cv = cacheable;
    131144        data.p = true;
    132145        data.w = true;
     
    134147
    135148        dtlb_data_in_write(data.value);
    136        
    137         /*
    138          * Quick hack: map keyboard
    139          */
    140         fr.address = KBD_PHYS_ADDRESS;
    141         pg.address = KBD_VIRT_ADDRESS;
    142 
    143         tag.value = ASID_KERNEL;
    144         tag.vpn = pg.vpn;
    145 
    146         dtlb_tag_access_write(tag.value);
    147 
    148         data.value = 0;
    149         data.v = true;
    150         data.size = PAGESIZE_8K;
    151         data.pfn = fr.pfn;
    152         data.l = true;
    153         data.cp = 0;
    154         data.cv = 0;
    155         data.p = true;
    156         data.w = true;
    157         data.g = true;
    158 
    159         dtlb_data_in_write(data.value);
    160149}
    161150
     
    170159{
    171160        tlb_tag_access_reg_t tag;
    172         tlb_data_t data;
    173161        __address tpc;
    174162        char *tpc_str;
     
    187175         * Identity map piece of faulting kernel address space.
    188176         */
    189         data.value = 0;
    190         data.v = true;
    191         data.size = PAGESIZE_8K;
    192         data.pfn = tag.vpn;
    193         data.l = false;
    194         data.cp = 1;
    195         data.cv = 1;
    196         data.p = true;
    197         data.w = true;
    198         data.g = true;
    199 
    200         dtlb_data_in_write(data.value);
     177        dtlb_insert_mapping(tag.vpn * PAGE_SIZE, tag.vpn * FRAME_SIZE, PAGESIZE_8K, false, true);
    201178}
    202179
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