Changeset 89c57b6 in mainline for kernel/arch/mips32/include/mm/tlb.h


Ignore:
Timestamp:
2011-04-13T14:45:41Z (14 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
88634420
Parents:
cefb126 (diff), 17279ead (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge mainline changes.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/mips32/include/mm/tlb.h

    rcefb126 r89c57b6  
    3939#include <arch/mm/asid.h>
    4040#include <arch/exception.h>
     41#include <trace.h>
    4142
    4243#define TLB_ENTRY_COUNT  48
     
    126127 * Probe TLB for Matching Entry.
    127128 */
    128 static inline void tlbp(void)
     129NO_TRACE static inline void tlbp(void)
    129130{
    130131        asm volatile ("tlbp\n\t");
     
    136137 * Read Indexed TLB Entry.
    137138 */
    138 static inline void tlbr(void)
     139NO_TRACE static inline void tlbr(void)
    139140{
    140141        asm volatile ("tlbr\n\t");
     
    145146 * Write Indexed TLB Entry.
    146147 */
    147 static inline void tlbwi(void)
     148NO_TRACE static inline void tlbwi(void)
    148149{
    149150        asm volatile ("tlbwi\n\t");
     
    154155 * Write Random TLB Entry.
    155156 */
    156 static inline void tlbwr(void)
     157NO_TRACE static inline void tlbwr(void)
    157158{
    158159        asm volatile ("tlbwr\n\t");
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